Re: [PATCH v4 2/2] arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Omission of `dma-coherent` property on SMMU-routed DMA master nodes (`usb0`, `dmac0`, `dmac1`) causes potential data corruption.
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commit d5421d52fec812147859d426e90e92990eb7c1b8
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes

The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
redundant cache flush/invalidate operations and potential stale data
issues.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 654f94ded1e85..3de424ae3b8ba 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -576,6 +576,7 @@ gmac0: ethernet@10810000 {
>  			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
>  			snps,clk-csr = <0>;
>  			iommus = <&smmu 1>;
> +			dma-coherent;
>  			status = "disabled";
>  
>  			stmmac_axi_emac0_setup: stmmac-axi-config {

[Severity: High]
This is a pre-existing issue, but since the commit message establishes that
transactions going through the SMMU are cache coherent, should the
dma-coherent property also be added to other SMMU-routed DMA master nodes?

Looking at arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi, the dmac0, dmac1,
and usb0 nodes also route through the SMMU but lack the dma-coherent property:

dmac0: dma-controller@0 {
        ...
        iommus = <&smmu 8>;
};

If the kernel incorrectly treats these devices as non-coherent, allocating
a DMA buffer for reading (DMA_FROM_DEVICE) might result in a cache
invalidation (DC IVAC via dmac_inv_range()) discarding dirty cache lines
without writing them back to memory.

This would cause the CPU to subsequently read stale data, permanently losing
the data the device just wrote.

Could this incomplete fix leave usb0, dmac0, and dmac1 vulnerable to data
corruption and loss?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260624062203.12221-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2