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From: sashiko-bot@kernel.org
To: "Ricardo Pardini via B4 Relay" <devnull+ricardo.pardini.net@kernel.org>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH] arm64: dts: mediatek: mt8395-radxa-nio-12l: Enable I2C3 on 40-pin header
Date: Wed, 24 Jun 2026 11:58:34 +0000	[thread overview]
Message-ID: <20260624115835.520C21F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260624-nio-12l-add-i2c-40-pin-v1-1-f6c11ed2184c@pardini.net>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Contradictory and invalid multiple drive strength properties (`drive-strength` and `drive-strength-microamp`) in the `i2c3_pins` pinctrl node.
--

commit cc885ce9bc43909e2fea294bb5532055037c4cf5
Author: Ricardo Pardini <ricardo@pardini.net>

arm64: dts: mediatek: mt8395-radxa-nio-12l: Enable I2C3 on 40-pin header

This commit enables I2C3 on the 40-pin header for the Radxa NIO 12L board.
It adds the corresponding pin configurations to allow users to connect
external I2C devices.

> diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
> index bf91305e8e4a5..03a2f2e746475 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts

[ ... ]

> @@ -789,6 +797,16 @@ pins-bus {
>  		};
>  	};
>  
> +	i2c3_pins: i2c3-pins {
> +		pins-bus {
> +			pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
> +				 <PINMUX_GPIO15__FUNC_SCL3>;
> +			bias-pull-up = <1000>;
> +			drive-strength = <6>;
> +			drive-strength-microamp = <1000>;

[Severity: Medium]
Is it expected to specify both drive-strength and drive-strength-microamp
for the same pins here?

The generic pinconf parser will emit a boot error log when it encounters
multiple drive strength properties, as requesting both 6mA and 1mA drive
strengths is contradictory.

Both properties will then propagate to the Mediatek pinctrl driver, which
may program both the standard and advanced driving circuits simultaneously.

Could this leave the I2C3 pins in an undefined electrical state?

> +		};
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260624-nio-12l-add-i2c-40-pin-v1-1-f6c11ed2184c@pardini.net?part=1

      reply	other threads:[~2026-06-24 11:58 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-24 11:41 [PATCH] arm64: dts: mediatek: mt8395-radxa-nio-12l: Enable I2C3 on 40-pin header Ricardo Pardini via B4 Relay
2026-06-24 11:58 ` sashiko-bot [this message]

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