Re: [PATCH v3 2/2] arm64: dts: socfpga: agilex72: Add initial device tree

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing CPU topology and relative capacity metrics (`capacity-dmips-mhz`) for the heterogeneous Cortex-A520/A720 cluster.
- [Medium] Malformed reserved-memory nodes for firmware regions mixing static and dynamic properties, and improperly exposing secure memory as a DMA pool.
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commit 24c23f8ecc00caa97660929277c73ae2d495bf92
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: agilex72: Add initial device tree

This commit adds initial device tree support for the Intel SoCFPGA Agilex72
platform. The Agilex72 SoC features a heterogeneous CPU cluster with
Cortex-A520 and Cortex-A720 cores, and includes an SMMU v3 for memory
management.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
> new file mode 100644
> index 0000000000000..c29c2afcaab70
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
> @@ -0,0 +1,156 @@
[ ... ]
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		atf_reserved: atf@80000000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x80000000 0x0 0x100000>;
> +			alignment = <0x1000>;
> +			no-map;
> +		};

[Severity: Medium]
Does this node improperly mix static and dynamic allocation properties?

The reg property implies static allocation, while alignment is for
dynamic allocation, and according to the bindings, these are mutually
exclusive.

Also, should ATF memory be exposed as a shared-dma-pool? Secure firmware
memory generally shouldn't be exposed as a pool for the kernel's DMA
subsystem to manage, as it could lead to exceptions if the non-secure kernel
attempts to map or allocate from it.

> +
> +		service_reserved: svcbuffer@80100000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x80100000 0x0 0xf00000>;
> +			alignment = <0x1000>;
> +			no-map;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a520";
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			reg = <0x0>;
> +		};

[Severity: Medium]
Will the scheduler treat these heterogeneous cores as having equal compute
capacity?

Without a cpu-map topology and capacity-dmips-mhz properties, the Linux
scheduler may default to treating the Cortex-A520 and Cortex-A720 cores
as having equal capacity.

This could lead to suboptimal task placement for the big.LITTLE
architecture.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260625065329.20274-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2