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[80.183.219.152]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-46e6167c05fsm9094388f8f.25.2026.06.26.02.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2026 02:20:41 -0700 (PDT) From: Christian Marangi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 0/4] PCI: mediatek-gen3: Add 2-lanes mode support + clock Date: Fri, 26 Jun 2026 11:20:24 +0200 Message-ID: <20260626092029.3525264-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This small series introduce support for 2-lanes mode for Airoha AN7581 SoC. This is needed for correctly functionality of Eagle WiFi Card normally attached to this SoC that require a 2-line PCIe card to correctly work (and give the proper performance) The first 2 patch address a limitation of the PCIe implementation where the PERSTOUT reset were indirectly asserted and deasserted all at the same time (for all the 3 PCIe card) with PCIe enable and disable. The 2 patch address this and introduce correct reset to control reset line for the relevant PCIe line. The last 2 patch add additional logic and support to assert and deassert the PERSTOUT and also apply the required configuration for 2-lanes mode. 2-lanes mode is implemented in DT by adding the required property and by defining the "num-lanes" to 2. Changes v2: - Address typo regs -> reg in Documentation - Address typo lan -> lane in Documentation - Apply a suggested fix from Airoha for PCIe MUX configuration before PHY init - Parse secondary reg in probe - Add missing reset_status handling for inverted bits - Move SCU to local handling in power_up - Add check for max num-lanes for EN7581 Christian Marangi (4): dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT clk: en7523: add support for dedicated PCIe PERSTOUT reset dt-bindings: PCI: mediatek-gen3: Split Airoha schema and document 2-lanes PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581 .../bindings/pci/airoha,en7581-pcie.yaml | 251 ++++++++++++++++++ .../bindings/pci/mediatek-pcie-gen3.yaml | 77 +----- drivers/clk/clk-en7523.c | 39 ++- drivers/pci/controller/pcie-mediatek-gen3.c | 101 +++++-- .../dt-bindings/reset/airoha,en7581-reset.h | 4 + 5 files changed, 370 insertions(+), 102 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml -- 2.53.0