Re: [PATCH v2 2/2] arm64: dts: ti: Add support for the phyCORE-AM67x

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The external PCIe reference clock generator `pcie_refclk0` is never selected as a clock parent, leaving the oscillator permanently disabled.
--

commit d9846b20b72a17d0a0d8f41ab892c88f00f2de4e
Author: Nathan Morrisson <nmorrisson@phytec.com>

arm64: dts: ti: Add support for the phyCORE-AM67x

Add support for the PHYTEC phyCORE-AM67x SoM and the corresponding
phyBOARD-Rigel carrier board. Features include audio playback, CAN,
PCIe, USB, eMMC, Ethernet, and various sensors.

[1] https://www.phytec.com/product/phycore-am67x/
[2] https://www.phytec.com/product/phyboard-am67x-development-kit/

> diff --git a/arch/arm64/boot/dts/ti/k3-am6754-phyboard-rigel.dts b/arch/arm64/boot/dts/ti/k3-am6754-phyboard-rigel.dts
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am6754-phyboard-rigel.dts

[ ... ]

> +&serdes1 {
> +	status = "okay";
> +
> +	serdes1_pcie_link: phy@0 {

[Severity: High]
Will pcie_refclk0 remain disabled here since assigned-clock-parents isn't
overridden?

The base SoC device tree configures the serdes1 node with
assigned-clock-parents = <&k3_clks 280 1> (the internal core_ref_clk).
While the board DTS provides pcie_refclk0 in the serdes_wiz1 clocks array
below, it doesn't appear to override assigned-clock-parents on &serdes1 to
actually select it.

Because the clock framework might retain the SoC's default internal clock,
the physical PCIe reference clock oscillator's GPIO gate is never asserted,
which could cause PCIe link training to fail.

> +		reg = <0>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_PCIE>;
> +		resets = <&serdes_wiz1 1>;
> +	};
> +};
> +
> +&serdes_wiz1 {
> +	clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&pcie_refclk0>;
> +	status = "okay";
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260626161014.1146128-1-nmorrisson@phytec.com?part=2