Re: [PATCH v2 3/3] arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The MCP251xFD CAN controller uses an active-low interrupt line that must be configured as level-triggered, but is configured as edge-triggered (`IRQ_TYPE_EDGE_FALLING`).
- [Low] The ads7846 touchscreen node uses deprecated properties.
- [Low] The pinmux `MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22` is configured as a GPIO in `pinctrl_ecspi1` but `GPIO4_IO22` is never used by `ecspi1` or any of its subnodes.
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commit bb01573339283cd17f8253331852c339f7a84276
Author: Stefano Radaelli <stefano.r@variscite.com>

arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board

Add device tree support for the Variscite Sonata carrier board with the
DART-MX8M-MINI system on module. This adds support for peripherals including
uSD Card, USB, UART, SPI, I2C, RTC, TPM, and CAN interfaces.

Link: https://variscite.com/carrier-boards/sonata-board/

> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
> new file mode 100644
> index 0000000000000..93b0076987b82
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
[ ... ]
> +	/* Resistive touch controller */
> +	ads7846: touchscreen@0 {
> +		compatible = "ti,ads7846";
> +		reg = <0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_restouch>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
> +		spi-max-frequency = <1500000>;
> +		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
> +		ti,x-min = /bits/ 16 <125>;
> +		ti,x-max = /bits/ 16 <4008>;
> +		ti,y-min = /bits/ 16 <282>;
> +		ti,y-max = /bits/ 16 <3864>;
> +		ti,x-plate-ohms = /bits/ 16 <180>;
> +		ti,pressure-max = /bits/ 16 <255>;
> +		ti,debounce-max = /bits/ 16 <10>;

[Severity: Low]
Are these specific ti,ads7846 properties deprecated in favor of generic
touchscreen properties? Using the standard generic bindings might avoid
device tree validation warnings.

> +		ti,debounce-tol = /bits/ 16 <3>;
> +		ti,debounce-rep = /bits/ 16 <1>;
> +		ti,settle-delay-usec = /bits/ 16 <150>;
> +		ti,keep-vref-on;
> +		wakeup-source;
> +	};
> +
> +	can0: can@1 {
> +		compatible = "microchip,mcp251xfd";
> +		reg = <1>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_can>;
> +		clocks = <&clk40m>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;

[Severity: High]
Does the mcp251xfd CAN controller require a level-triggered interrupt rather
than edge-triggered? If the device holds the INT pin low while internal
interrupts are pending, an edge-triggered setup might miss subsequent
interrupts if the line does not transition high to low again, potentially
stalling CAN communication.

[ ... ]
> +	pinctrl_captouch: captouchgrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x16
> +		>;
> +	};
> +
> +	pinctrl_ecspi1: ecspi1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
> +			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
> +			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
> +			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x13
> +			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x13
> +			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x13

[Severity: Low]
Is MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 used by ecspi1 or its subnodes? It
appears to be included in the pinctrl_ecspi1 group without being referenced
by the SPI interface, which could unnecessarily claim the pad or cause
conflicts.

> +		>;
> +	};
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782571383.git.stefano.r@variscite.com?part=3