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Sat, 27 Jun 2026 22:36:36 -0700 (PDT) From: Kurt Borja Date: Sun, 28 Jun 2026 00:36:06 -0500 Subject: [PATCH v2 5/7] iio: adc: ti-ads1262: Add conversion delay support Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260628-ads126x-v2-5-4b1b231325ba@gmail.com> References: <20260628-ads126x-v2-0-4b1b231325ba@gmail.com> In-Reply-To: <20260628-ads126x-v2-0-4b1b231325ba@gmail.com> To: Kurt Borja , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner Cc: =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4445; i=kuurtb@gmail.com; h=from:subject:message-id; bh=wB1Of1Emb/yY9dOSMsbzG5YZygdOZKgZHPMDGP/bhpU=; b=owGbwMvMwCUmluBs8WX+lTTG02pJDFkOm278yc1c6fU9dP4EnjeTWPRcrsncCLe9/PbgPYapO qm6ytumdZSyMIhxMciKKbK0Jyz69igq763fgdD7MHNYmUCGMHBxCsBEPh1i+B+6LOhYX0f1Wmnl 44c1uW1VNP691cr9kuLBUhf29rhioRzD/wD9lTGTt+3y2n9adtrEBgvuHukzoszfRCcvzmhgbxf sYQQA X-Developer-Key: i=kuurtb@gmail.com; a=openpgp; fpr=54D3BE170AEF777983C3C63B57E3B6585920A69A Expose the programmable conversion start delay as a per-channel IIO_CHAN_INFO_CONVDELAY attribute. Signed-off-by: Kurt Borja --- drivers/iio/adc/ti-ads1262.c | 63 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ti-ads1262.c b/drivers/iio/adc/ti-ads1262.c index 8921eaae537f6b0a..4ae22c1b0b4b7d79 100644 --- a/drivers/iio/adc/ti-ads1262.c +++ b/drivers/iio/adc/ti-ads1262.c @@ -141,6 +141,21 @@ #define ADS1262_MAX_CHANNEL_COUNT 16 #define ADS1262_XFER_BUFFER_SZ 11 +enum { + ADS1262_DELAY_NO_DELAY, + ADS1262_DELAY_8700_NS, + ADS1262_DELAY_17_US, + ADS1262_DELAY_35_US, + ADS1262_DELAY_69_US, + ADS1262_DELAY_139_US, + ADS1262_DELAY_278_US, + ADS1262_DELAY_555_US, + ADS1262_DELAY_1100_US, + ADS1262_DELAY_2200_US, + ADS1262_DELAY_4400_US, + ADS1262_DELAY_8800_US, +}; + enum { ADS1262_RUNMODE_CONTINUOUS, ADS1262_RUNMODE_PULSE, @@ -225,6 +240,7 @@ struct ads1262_chip_info { struct ads1262_channel { u8 input[2]; + u8 delay; u8 filter; u8 gain; u8 data_rate; @@ -281,6 +297,21 @@ static const int ads1262_data_rate_avail[][2] = { [ADS1262_DR_38400_SPS] = { 38400, 0 }, }; +static const int ads1262_conv_delay_avail[][2] = { + [ADS1262_DELAY_NO_DELAY] = { 0, 0 }, + [ADS1262_DELAY_8700_NS] = { 0, 8700 }, + [ADS1262_DELAY_17_US] = { 0, 17000 }, + [ADS1262_DELAY_35_US] = { 0, 35000 }, + [ADS1262_DELAY_69_US] = { 0, 69000 }, + [ADS1262_DELAY_139_US] = { 0, 139000 }, + [ADS1262_DELAY_278_US] = { 0, 278000 }, + [ADS1262_DELAY_555_US] = { 0, 555000 }, + [ADS1262_DELAY_1100_US] = { 0, 1100000 }, + [ADS1262_DELAY_2200_US] = { 0, 2200000 }, + [ADS1262_DELAY_4400_US] = { 0, 4400000 }, + [ADS1262_DELAY_8800_US] = { 0, 8800000 }, +}; + static const int ads1262_pga_gain_avail[] = { 1, 2, 4, 8, 16, 32 }; @@ -473,7 +504,8 @@ static int ads1262_channel_enable(struct ads1262 *st, /* Avoid using guard() here to mitigate AB/BA deadlock warning */ mutex_lock(&st->chan_lock); - mode0 = FIELD_PREP(ADS1262_MODE0_INPUT_CHOP_MASK, chan->input_chop) | + mode0 = FIELD_PREP(ADS1262_MODE0_DELAY_MASK, chan->delay) | + FIELD_PREP(ADS1262_MODE0_INPUT_CHOP_MASK, chan->input_chop) | FIELD_PREP(ADS1262_MODE0_IDAC_CHOP_MASK, chan->idac_chop) | FIELD_PREP(ADS1262_MODE0_REFREV_MASK, chan->ref_reversal); mode1 = FIELD_PREP(ADS1262_MODE1_FILTER_MASK, chan->filter); @@ -491,6 +523,7 @@ static int ads1262_channel_enable(struct ads1262 *st, mutex_unlock(&st->chan_lock); ret = regmap_update_bits(st->regmap, ADS1262_MODE0_REG, + ADS1262_MODE0_DELAY_MASK | ADS1262_MODE0_INPUT_CHOP_MASK | ADS1262_MODE0_IDAC_CHOP_MASK | ADS1262_MODE0_REFREV_MASK, mode0); @@ -625,6 +658,15 @@ static int ads1262_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT_PLUS_MICRO; } + case IIO_CHAN_INFO_CONVDELAY: { + guard(mutex)(&st->chan_lock); + + *val = ads1262_conv_delay_avail[chan_data->delay][0]; + *val2 = ads1262_conv_delay_avail[chan_data->delay][1]; + + return IIO_VAL_INT_PLUS_NANO; + } + default: return -EOPNOTSUPP; } @@ -647,6 +689,12 @@ static int ads1262_read_avail(struct iio_dev *indio_dev, *length = ARRAY_SIZE(ads1262_pga_gain_avail); return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_CONVDELAY: + *type = IIO_VAL_INT_PLUS_NANO; + *vals = (const int *)ads1262_conv_delay_avail; + *length = ARRAY_SIZE(ads1262_conv_delay_avail) * 2; + return IIO_AVAIL_LIST; + default: return -EOPNOTSUPP; } @@ -685,6 +733,17 @@ static int ads1262_write_raw(struct iio_dev *indio_dev, break; } + case IIO_CHAN_INFO_CONVDELAY: { + i = ads1262_find_two(ads1262_conv_delay_avail, val, val2); + if (i < 0) + return i; + + guard(mutex)(&st->chan_lock); + chan_data->delay = i; + + break; + } + default: return -EOPNOTSUPP; } @@ -807,8 +866,10 @@ static int ads1262_alloc_channels(struct ads1262 *st, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_HARDWAREGAIN) | + BIT(IIO_CHAN_INFO_CONVDELAY) | BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_shared_by_type_available = + BIT(IIO_CHAN_INFO_CONVDELAY) | BIT(IIO_CHAN_INFO_HARDWAREGAIN) | BIT(IIO_CHAN_INFO_SAMP_FREQ), .indexed = true, -- 2.54.0