Re: [PATCH 3/5] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incorrect 'reg' size property (0xffff instead of 0x10000) for the SerDes blocks, improperly sizing the memory region and missing its last byte.
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commit e38fd823b92e0ac25dfc572821e4084ac6569201
Author: Vladimir Oltean <vladimir.oltean@nxp.com>

arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks

This patch describes the two Lynx 10G SerDes blocks and their associated lanes
found on the LS1046A SoC. The nodes are initially left disabled at the SoC
level.

> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index 6fefe837f434f..db935805c3792 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -424,6 +424,66 @@ sfp: efuse@1e80000 {
>  			clock-names = "sfp";
>  		};
>  
> +		serdes1: phy@1ea0000 {
> +			compatible = "fsl,ls1046a-serdes1";
> +			reg = <0x00 0x1ea0000 0x0 0xffff>;

[Severity: Low]
Is the region size of 0xffff correct here? 

The reg property typically specifies the total size of the block, not the
maximum offset. Should this be 0x10000 to cover the full 64KB block and
include the final byte of the hardware region?

> +			#address-cells = <1>;
> +			#size-cells = <0>;

[ ... ]

> +		serdes2: phy@1eb0000 {
> +			compatible = "fsl,ls1046a-serdes2";
> +			reg = <0x00 0x1eb0000 0x0 0xffff>;

[Severity: Low]
Similarly, does the serdes2 block also need a reg size of 0x10000 instead of
0xffff?

> +			#address-cells = <1>;
> +			#size-cells = <0>;

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260630110459.516364-1-ioana.ciornei@nxp.com?part=3