From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69711362153; Wed, 1 Jul 2026 16:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782922130; cv=none; b=DE58ofApamaLq5QFu9fegO+1awFWDJWJIpTn6w0TCCyNZj1KTnpBmlEeFJ9bFJ794XLf06jmjKVd5HEWRbRuEYrYAJ6v9NyWfDOY09NyZ2bczRnE8vXEdznqrgHNKgzeXkaTN2ewOYRqcEGKGiFZMdkZ7moTZDDJwiRQ+diJTsI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782922130; c=relaxed/simple; bh=7x90ve23SMkp3Rl+jh7oopqEDI3U6YIVoFgiSKuoy/U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W3Kbctvvz0eeJJuzSZawiNJvhyT3XiF/JKeyZQe++51DOThDk73xGWGCkBNpLANHFPN0qlsG/cbN7pNjh2HbaRIU3zEEfhSrxgIRQwEc8TweUVa23vTKJX1jSMLbgfuwPJ9HfkDVYdoRR6zMs0jLAyH5d87NXDmtEfB1nCga4Gw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HqY9lwvP; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HqY9lwvP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3F4B91F00A3D; Wed, 1 Jul 2026 16:08:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1782922127; bh=ilf76DE9BP6bAlpJ5TSsK+VG1K4+DBYU3ah/k09fSb0=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=HqY9lwvPhjcZO2a+SqiUelb3CqZVUPmbrWLT4/cTDap+EVImbQAvCUP0R2SM/WZQO Scd4yskDCD+2YKNAvZbcZ7K44rCMHwXW4lN3g4AXY4Hse6YFG7YRYASCFhanzLUnI1 LzDKQ3jMd9G21k+LviG+9DwalATXAuXQ7AZwv8uOHJ1IDwuQqK0oUEPvbG2Opyv7GP rI8fxYeaQYOFBJBkbdlJ8LjAaujlFThtFwwZCo9sG5WuQEfqyMTTnhaXfq+Ii6DKTA qhu1SsTq3uuz2N+ZB3Tt5wDAP3gd411xwPtTX2p5Q7SOmKfVMAruhokttbNwUAnmNJ eL1tBI1vme29g== From: Thierry Reding Date: Wed, 01 Jul 2026 18:08:13 +0200 Subject: [PATCH v3 02/11] dt-bindings: display: tegra: Document memory regions Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260701-tegra-vpr-v3-2-d80f7b871bb4@nvidia.com> References: <20260701-tegra-vpr-v3-0-d80f7b871bb4@nvidia.com> In-Reply-To: <20260701-tegra-vpr-v3-0-d80f7b871bb4@nvidia.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Sowjanya Komatineni , Luca Ceresoli , Mikko Perttunen , Yury Norov , Rasmus Villemoes , Russell King , Alexander Gordeev , Gerald Schaefer , Heiko Carstens , Vasily Gorbik , Christian Borntraeger , Sven Schnelle , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , "Liam R. Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Marek Szyprowski , Robin Murphy , Sumit Semwal , Benjamin Gaignard , Brian Starkey , John Stultz , "T.J. Mercier" , =?utf-8?q?Christian_K=C3=B6nig?= , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers , Catalin Marinas , Will Deacon Cc: Thierry Reding , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-s390@vger.kernel.org, linux-mm@kvack.org, iommu@lists.linux.dev, linaro-mm-sig@lists.linaro.org, linux-trace-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3570; i=treding@nvidia.com; h=from:subject:message-id; bh=GRoiIFMQfM7gzDRzAuvdY2P5ccmj+ETXrFNLv78LxOI=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqRTuFSGQ9dGDN3kzOm9qzarxw9OZw0cL6HePrk 0Jmuoyl0AuJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCakU7hQAKCRDdI6zXfz6z oS/+EAC0wB3gChuITlH2sXNXS95V4q3MybbSfE5oD4mkn+StZvm3vAI3H6Wdr6rx8fe60LuedY1 ghz5YAwiKSOdYiM6OfwagrwPDHgHQVSk3E4CPqiABKXW4cWQrj45IrvuYUv74j4XLe4d86wLPEc XRhz4WxuobfKAmeCp+vP/1AGwYm31jnYqxiEGYGwGax8B/QNjsTHDmN/l8yN0gSCAan2Ebbl6Db B8Y0tocMlvJfkN9Vpy+I8CLl1NVGl8fFDR4rjlxNPMqrXh35zmG9tFZoUZKrXh3gkSueSWXm3Ic dc2rrIVfCdZWUyVVQP3HYvlG3o7ZYoBFQkR9Dgb5utSERxWZywX9+WhXOsfwMTecDydnHHLp9QX 90ACCc5x14rRGWrNQIlX+ybDXW8xM5UH9lHkjZh+d0I2aRyPG+qVnPAuVTSf0X+oVb0gOk853fu g7nObP5ggkU3TL1+l0JvQElWXT27M27tvn33q83T6T1naf8aBXCVi4yvgiz/XxsDYtVZGzCE4c2 8oAnmE+ODLePWMnjAD4liqDajcrofCGaaFuwfGSS30RLIFzaTXxEV5cO2Im7VmVd5cB5Z0riYPB dC4NBuEohrV4cIXBZF9s7vfDIUwZIrcmM41FJPTZ2/Xztxqx9yXCYp3SPR5pN1JqKkpvf+/TC/S 34uWCUo4nfgROIg== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Add the memory-region and memory-region-names properties to the bindings for the display controllers and the host1x engine found on various Tegra generations. These memory regions are used to access firmware-provided framebuffer memory as well as the video protection region. Signed-off-by: Thierry Reding --- Changes in v3: - document properties for VIC --- .../devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml | 8 ++++++++ .../devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml | 10 ++++++++++ .../devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml | 10 +++++++++- .../bindings/display/tegra/nvidia,tegra20-host1x.yaml | 7 +++++++ 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml index 7200095ef19e..1e27a731ad9a 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml @@ -67,6 +67,14 @@ properties: - const: dma-mem # read - const: write + memory-region: + items: + - description: reference to the video protection memory region + + memory-region-names: + items: + - const: protected + dma-coherent: true additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml index ce4589466a18..881bfbf4764d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml @@ -57,6 +57,16 @@ properties: - const: dma-mem # read-0 - const: read-1 + memory-region: + minItems: 1 + maxItems: 2 + + memory-region-names: + items: + enum: [ framebuffer, protected ] + minItems: 1 + maxItems: 2 + nvidia,outputs: description: A list of phandles of outputs that this display controller can drive. diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml index 69be95afd562..a012644eeb7d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml @@ -65,7 +65,15 @@ properties: items: - description: phandle to the core power domain - memory-region: true + memory-region: + minItems: 1 + maxItems: 2 + + memory-region-names: + items: + enum: [ framebuffer, protected ] + minItems: 1 + maxitems: 2 nvidia,head: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml index 3563378a01af..f45be30835a8 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml @@ -96,6 +96,13 @@ properties: items: - description: phandle to the HEG or core power domain + memory-region: + maxItems: 1 + + memory-region-names: + items: + - const: protected + required: - compatible - interrupts -- 2.54.0