Re: [PATCH v6 6/7] pwm: tegra: Add support for Tegra264

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing initialization of CSR_1.DEPTH for Tegra264 can cause incorrect PWM frequency and duty cycle if the hardware reset state or bootloader configuration is not 255.
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commit 3a866062b05a26bd8399e91a9683b58d16e08587
Author: Mikko Perttunen <mperttunen@nvidia.com>

pwm: tegra: Add support for Tegra264

This commit adds support for the Tegra264 PWM controller. It introduces
handling for a new register layout where the enable bit is moved to a
separate CSR_1 register.

> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index ad75e4ee34102..5cdbe120ba2d8 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c

[ ... ]

> @@ -215,6 +257,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>  
>  static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>  {
> +	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
>  	int rc = 0;
>  	u32 val;
>  
> @@ -222,20 +265,21 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>  	if (rc)
>  		return rc;
>  
> -	val = tegra_pwm_readl(pwm, TEGRA_PWM_CSR_0);
> +	val = tegra_pwm_readl(pwm, pc->soc->enable_reg);
>  	val |= TEGRA_PWM_ENABLE;
> -	tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val);
> +	tegra_pwm_writel(pwm, pc->soc->enable_reg, val);

[Severity: Medium]
Will this lead to incorrect PWM frequency and duty cycle if the hardware
or bootloader does not initialize the DEPTH field to 255?

Since CSR_1 is read-modify-written here to set the enable bit, the DEPTH
field (bits 30:15) is left uninitialized and relies on the pre-existing
state from the bootloader or hardware defaults. 

However, in tegra_pwm_config(), the driver calculates the frequency
divider and duty cycle assuming a hardcoded depth of 256:

tegra_pwm_config()
    ...
    c *= TEGRA_PWM_DEPTH;
    c = DIV_ROUND_CLOSEST_ULL(c, period_ns);

If CSR_1.DEPTH is not set to 255 (which corresponds to a hardware depth
divisor of 256), could this mismatch result in incorrect frequencies
or clipping of the output duty cycle?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260701-t264-pwm-v6-0-2718f61f411f@nvidia.com?part=6