Re: [PATCH 1/1] arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The `gpio-ranges` property incorrectly exposes non-existent pins by spanning across an unmapped hardware gap.
- [Low] The patch adds new properties and expands the `reg` array without updating the corresponding device tree schema.
--

commit affdc0c44669a05cd149cc0e3b877996d58cc004
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>

arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl node

Update the SIUL2 pinctrl node to describe the additional register ranges and
DT properties used by the updated SIUL2 driver. This includes PGPDO and
PGPDI registers for GPIO operations and an EIRQ register window for interrupts.

> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -135,7 +135,26 @@ pinctrl: pinctrl@4009c240 {
>  				/* IMCR119-IMCR397 registers on siul2_1 */
>  			      <0x44010c1c 0x45c>,
>  				/* IMCR430-IMCR495 registers on siul2_1 */
> -			      <0x440110f8 0x108>;
> +			      <0x440110f8 0x108>,
> +				/* PGPDO registers on siul2_0 */
> +			      <0x4009d700 0x10>,

[Severity: Low]
Is there an accompanying update to the device tree schema? 

Adding these new properties and expanding the reg array to 11 items without 
updating the nxp,s32g2-siul2-pinctrl.yaml schema will likely cause 
make dtbs_check to fail with validation errors.

> +				/* PGPDI registers on siul2_0 */
> +			      <0x4009d740 0x10>,

[ ... ]

> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pinctrl 0 0 102>,
> +					<&pinctrl 112 112 79>;

[Severity: Medium]
Does this 79-pin span expose phantom GPIOs?

It appears this range spans across an unmapped hardware gap, which would expose
21 phantom GPIOs (123-143) to userspace. Attempting to request them from userspace
would fail with -EINVAL.

Should this be split into 11 and 47 pin ranges to account for the 21-pin gap?

> +
> +			interrupt-controller;

[ ... ]

> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -193,7 +193,26 @@ pinctrl: pinctrl@4009c240 {
>  				/* IMCR119-IMCR397 registers on siul2_1 */
>  			      <0x44010c1c 0x45c>,
>  				/* IMCR430-IMCR495 registers on siul2_1 */
> -			      <0x440110f8 0x108>;
> +			      <0x440110f8 0x108>,
> +				/* PGPDO registers on siul2_0 */
> +			      <0x4009d700 0x10>,

[Severity: Low]
Does the nxp,s32g2-siul2-pinctrl.yaml schema need updating here as well to
prevent dtbs_check validation errors?

> +				/* PGPDI registers on siul2_0 */
> +			      <0x4009d740 0x10>,

[ ... ]

> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pinctrl 0 0 102>,
> +					<&pinctrl 112 112 79>;

[Severity: Medium]
Will this similarly expose the unmapped hardware gap and present phantom GPIOs
to userspace?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260701115120.1115494-2-khristineandreea.barbulescu@oss.nxp.com?part=1