From: sashiko-bot@kernel.org
To: "Guodong Xu" <docular.xu@gmail.com>
Cc: kvm@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v5 10/17] riscv: Add Zic64b to cpufeature and hwprobe
Date: Wed, 01 Jul 2026 13:53:57 +0000 [thread overview]
Message-ID: <20260701135357.E8CE91F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260701-rva23u64-hwprobe-v2-v5-10-2c61f94a695a@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The Zic64b extension is exported to userspace via hwprobe but lacks corresponding KVM support, preventing VMMs from discovering and exposing it to guests.
--
commit 071fffe45b5cfa38ee92c48f5063587d8cccb183
Author: Qingwei Hu <qingwei.hu@bytedance.com>
riscv: Add Zic64b to cpufeature and hwprobe
This commit adds support for the Zic64b extension to cpufeature and hwprobe.
It introduces a validation callback to ensure consistent CBO block sizes and
exports the capability to userspace.
Link: https://lists.riscv.org/g/tech-unprivileged/topic/question_about_zic64b_and/119631059
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 430dc49a82863..36ec8ab470423 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -122,6 +122,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZICCRSE (1ULL << 4)
> #define RISCV_HWPROBE_EXT_ZA64RS (1ULL << 5)
> #define RISCV_HWPROBE_EXT_B (1ULL << 6)
> +#define RISCV_HWPROBE_EXT_ZIC64B (1ULL << 7)
[Severity: Medium]
Since Zic64b is being exported to userspace via hwprobe here, should it also
be added to the KVM UAPI?
Without corresponding KVM support in enum KVM_RISCV_ISA_EXT_ID in
arch/riscv/include/uapi/asm/kvm.h and kvm_isa_ext_arr in arch/riscv/kvm/isa.c,
VMMs will be unable to negotiate and expose this capability to guests.
Does this patch need parallel KVM API plumbing to ensure virtualization
parity for this mandatory extension?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260701-rva23u64-hwprobe-v2-v5-0-2c61f94a695a@gmail.com?part=10
next prev parent reply other threads:[~2026-07-01 13:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-01 12:52 [PATCH v5 00/17] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-07-01 12:52 ` [PATCH v5 01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically Guodong Xu
2026-07-01 12:52 ` [PATCH v5 02/17] riscv: hwprobe.rst: Make indentation consistent Guodong Xu
2026-07-01 12:52 ` [PATCH v5 03/17] riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP Guodong Xu
2026-07-01 12:52 ` [PATCH v5 04/17] riscv: Standardize extension capitalization Guodong Xu
2026-07-01 12:52 ` [PATCH v5 05/17] riscv: Add Zicclsm to cpufeature and hwprobe Guodong Xu
2026-07-01 12:52 ` [PATCH v5 06/17] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs " Guodong Xu
2026-07-01 12:52 ` [PATCH v5 07/17] riscv: Add B to hwcap " Guodong Xu
2026-07-01 13:27 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 08/17] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz Guodong Xu
2026-07-01 13:35 ` sashiko-bot
2026-07-01 15:54 ` Rob Herring (Arm)
2026-07-01 20:39 ` Conor Dooley
2026-07-01 12:52 ` [PATCH v5 09/17] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-07-01 13:42 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 10/17] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-07-01 13:53 ` sashiko-bot [this message]
2026-07-01 12:52 ` [PATCH v5 11/17] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-07-01 12:52 ` [PATCH v5 12/17] riscv: dts: spacemit: k1: " Guodong Xu
2026-07-01 14:00 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 13/17] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-07-01 12:52 ` [PATCH v5 14/17] riscv: Add a getter for user PMLEN support Guodong Xu
2026-07-01 12:52 ` [PATCH v5 15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-07-01 14:22 ` sashiko-bot
2026-07-01 12:52 ` [PATCH v5 16/17] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-07-01 12:52 ` [PATCH v5 17/17] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
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