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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-66624021a75sm1354880d50.11.2026.07.02.10.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 10:10:23 -0700 (PDT) From: Enzo Adriano To: Junhui Liu Cc: Andre Przywara , Brian Masney , Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 4/8] clk: sunxi-ng: a733: Add PLL clocks support Date: Thu, 2 Jul 2026 13:10:20 -0400 Message-ID: <20260702171020.836546-1-enzo.adriano.code@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260310-a733-clk-v1-4-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-4-36b4e9b24457@pigmoral.tech> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Junhui, Register check for the PLLs against the public A733 User Manual V0.92: 13 of the 14 PLL control registers match the manual's offsets (PLL_DDR 0x0020 through PLL_DE 0x02E0, section 4.1.6.1 onwards). The one exception is pll-ref at 0x0000: the manual's CCU register list starts at 0x0020 (PLL_DDR), so the PLL_REF control register is not in the public V0.92 document. It does match the vendor kernel's CCU (SUN60IW2_PLL_REF_CTRL_REG 0x0000), so a short provenance note near the definition might help future readers, same as for the other vendor-sourced entries discussed in this thread. For what it's worth, on a Radxa Cubie A7S (26 MHz DCXO) we can confirm at runtime that pll-ref produces the normalized 24 MHz reference with the hosc-side clocks reading 26 MHz, so the modeling demonstrably works on hardware. Thanks, Enzo