From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58BA7417343; Fri, 3 Jul 2026 15:22:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783092161; cv=none; b=pRdy6IIY6y2KY7hxkxrnDHZHMgNns6xNgjjMsljZgcZ4Opcy7x01f42FdR02YhqcvfQSyzct1XSFw2CgXl8gwQLNZ3KysIN9C6dDN+0Akp8ndErmND5nbvUYTs5iG9/PLbkVzyud4FKExGt7CbeQ+2XkIGx8VwqdfUMxfih1beY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783092161; c=relaxed/simple; bh=rkby9DTuDlWpkTpLG2+FpCRRYcUgeEYZ68nXgMndy6c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bz5SFQkH5H5fUivgKA2LLUssN17GY9PeS3AZ/L8IJBSyaazFAiTF2W/13EvlOEHToB8+ynjew+OJ66zj+NART71590v9JybVRhLFq6bvoUFBjFf5xB5ugbsr1Wk9rcN/55hxOmFtA/LMwSJpO25+f2BrczquvHPJSLPR+z8Sgqk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=m/nD8Bjg; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="m/nD8Bjg" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id DD628C49F57; Fri, 3 Jul 2026 15:22:50 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0E88E60300; Fri, 3 Jul 2026 15:22:39 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 288F9104C95AF; Fri, 3 Jul 2026 17:22:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1783092157; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=2Wgl959xb8+oqY9lR21TC/PdtCjARt/8c5OlJzNQKns=; b=m/nD8BjgIbbxTJ6K8dVi0HdS2PO3bGtOEHQOcg9wEXWK3KOKvYnAjRwbUfM9SGuP7tZXZf TlDasXXyjEnq/E6x/HLVgoDX9wCB3wm9PXL5UCY7oMZxN/ZseTe8q1mIGQiGjpBajOzFqm zrlhNQ0v00IOj/SbNp+yOXhsbB4/v9MBdYoEvVcJVcCtHVp6z3/Ol0b7HJWCj8nS8/Jdll JnHeecmR1DL8ZHUvJI3Gy9egV1a6o73+8MDX5wrVzI75Gc5qus1gAu60L1Aa/yQHH+WWfp 9VIu1vpCTAom8VteUyv1+uI9Vpvw+m4ET5qoxwR9BQhXyYpoX6++KfGxtABiww== From: Richard Genoud To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Michael Turquette , Stephen Boyd , Brian Masney Cc: Paul Kocialkowski , Thomas Petazzoni , John Stultz , Joao Schim , bigunclemax@gmail.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Richard Genoud Subject: [PATCH v7 3/4] arm64: dts: allwinner: h616: add PWM controller Date: Fri, 3 Jul 2026 17:22:14 +0200 Message-ID: <20260703152215.192859-4-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260703152215.192859-1-richard.genoud@bootlin.com> References: <20260703152215.192859-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 The H616 has a PWM controller that can provide PWM signals, but also plain clocks. Add the PWM controller node and pins in the device tree. Tested-by: John Stultz Signed-off-by: Richard Genoud --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 1598e86259ab..90fe56a1d3cd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -281,6 +281,17 @@ watchdog: watchdog@30090a0 { clocks = <&osc24M>; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h616-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + #clock-cells = <1>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h616-pinctrl"; reg = <0x0300b000 0x400>; @@ -385,6 +396,42 @@ nand_rb1_pin: nand-rb1-pin { bias-pull-up; }; + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PD28"; + function = "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PG19"; + function = "pwm1"; + }; + + /omit-if-no-ref/ + pwm2_pin: pwm2-pin { + pins = "PH2"; + function = "pwm2"; + }; + + /omit-if-no-ref/ + pwm3_pin: pwm3-pin { + pins = "PH0"; + function = "pwm3"; + }; + + /omit-if-no-ref/ + pwm4_pin: pwm4-pin { + pins = "PI14"; + function = "pwm4"; + }; + + /omit-if-no-ref/ + pwm5_pin: pwm5-pin { + pins = "PA12"; + function = "pwm5"; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins = "PC0", "PC2", "PC4"; -- 2.47.3