Re: [PATCH v2 2/2] arm64: dts: axiado: Add initial support for AX3005 SoC and eval board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Shared `cpu-release-addr` across secondary CPUs violates arm64 spin-table semantics and causes SMP boot panics.
- [Low] The `gic500` node contains address translation properties without any child nodes, causing dtbs_check schema warnings.
--

commit 98da4ec387872dcf54e685ea2615453187fb1582
Author: Swark Yang <syang@axiado.com>

arm64: dts: axiado: Add initial support for AX3005 SoC and eval board
    
Add initial device tree support for the AX3005 SoC and its evaluation
board. The AX3005 is a multi-core SoC featuring 4 Cortex-A53 cores, and
this adds the CPUs, timer, GPIO, UART, I2C, I3C, SPI and USB controllers.

> diff --git a/arch/arm64/boot/dts/axiado/ax3005.dtsi b/arch/arm64/boot/dts/axiado/ax3005.dtsi
> new file mode 100644
> index 0000000000000..c3c66634d7774
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/ax3005.dtsi
[ ... ]
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x0>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x80002fa0>;
[ ... ]
> +		cpu1: cpu@1 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0 0x1>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x80002fa0>;

[Severity: High]
Since all secondary CPUs share this exact same release address, won't they
all wake up simultaneously on the first sev() instruction broadcast?

The standard arm64 spin-table implementation expects a unique release
address per CPU. If multiple CPUs wake concurrently and branch to
secondary_startup(), won't they race to use the single secondary_data
context and corrupt the stack?

If the AX3005 platform specification mandates a shared address, does this
platform need a custom enable-method or PSCI instead of spin-table?

[ ... ]
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		interrupt-parent = <&gic500>;
> +		ranges;
> +
> +		gic500: interrupt-controller@40400000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0x0 0x40400000 0x0 0x10000>,
> +			      <0x0 0x40500000 0x0 0xc0000>;
> +			ranges;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			#address-cells = <2>;
> +			#size-cells = <2>;

[Severity: Low]
Are these bus translation properties necessary here?

Since the gic500 node has no child nodes (like an ITS subnode), including
ranges, #address-cells, and #size-cells will trigger dtbs_check schema
warnings for arm,gic-v3.

> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> +			#redistributor-regions = <1>;
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260705-upstream-axiado-ax3005-upstream-v2-0-2dfbd1448f81@axiado.com?part=2