Re: [PATCH v2 8/8] riscv: dts: eswin: add watchdog support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Incorrect mapping of the APB clock (PCLK) to the timer reference clock (tclk), omitting the actual reference clock.
- [Low] Missing space after the '=' sign in the 'clocks' properties.
--

commit e654cdc83801a14778ef2783efed381807629c6f
Author: Pritesh Patel <pritesh.patel@einfochips.com>

riscv: dts: eswin: add watchdog support

This commit adds watchdog nodes for the ESWIN EIC7700 SoC and enables them
for the HiFive Premier P550 board.

[ ... ]

> diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> index 6d328befc623d..d079bb337ecbb 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> @@ -265,6 +265,46 @@ hsp_sp_csr: hsp-sp-top-csr@50440000 {
>  			};
>  		};
>  
> +		wdt0: watchdog@50800000 {
> +			compatible = "snps,dw-wdt";
> +			reg = <0x0 0x50800000 0x0 0x4000>;
> +			interrupts = <87>;
> +			clocks =<&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>;
                                ^^^^

[Severity: Low]
This isn't a bug, but there appears to be a missing space after the '=' sign.

> +			clock-names = "tclk";

[Severity: High]
Are we assigning the APB clock (PCLK) to the timer reference clock (tclk)
while omitting the actual reference clock (NOC_WDREF)?

The snps,dw-wdt driver retrieves tclk to determine the frequency for TOP
calculations and to enable the clock. Because EIC7700_CLK_GATE_LSP_WDT0_PCLK
is assigned to tclk here instead of the explicit watchdog reference clock
(EIC7700_CLK_GATE_NOC_WDREF), the driver might calculate timeouts using the
wrong rate and fail to enable NOC_WDREF entirely.

> +			resets = <&reset EIC7700_RESET_WDT0>;
> +			status = "disabled";
> +		};
> +
> +		wdt1: watchdog@50804000 {
> +			compatible = "snps,dw-wdt";
> +			reg = <0x0 0x50804000 0x0 0x4000>;
> +			interrupts = <88>;
> +			clocks =<&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>;
                                ^^^^

[Severity: Low]
This isn't a bug, but there is a missing space after the '=' sign here as
well.

> +			clock-names = "tclk";

[Severity: High]
Could this result in similar incorrect timeout calculations for wdt1 due to
omitting NOC_WDREF?

> +			resets = <&reset EIC7700_RESET_WDT1>;
> +			status = "disabled";
> +		};
> +
> +		wdt2: watchdog@50808000 {
> +			compatible = "snps,dw-wdt";
> +			reg = <0x0 0x50808000 0x0 0x4000>;
> +			interrupts = <89>;
> +			clocks =<&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>;
                                ^^^^

[Severity: Low]
This isn't a bug, but there is a missing space after the '=' sign.

> +			clock-names = "tclk";

[Severity: High]
Does this node also need NOC_WDREF to avoid incorrect timeout calculations?

> +			resets = <&reset EIC7700_RESET_WDT2>;
> +			status = "disabled";
> +		};
> +
> +		wdt3: watchdog@5080c000 {
> +			compatible = "snps,dw-wdt";
> +			reg = <0x0 0x5080c000 0x0 0x4000>;
> +			interrupts = <90>;
> +			clocks =<&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>;
                                ^^^^

[Severity: Low]
This isn't a bug, but there is a missing space after the '=' sign.

> +			clock-names = "tclk";

[Severity: High]
Is the explicit watchdog reference clock (NOC_WDREF) missing for wdt3 as
well?

> +			resets = <&reset EIC7700_RESET_WDT3>;
> +			status = "disabled";
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260706081055.1126275-1-pinkesh.vaghela@einfochips.com?part=8