Re: [PATCH 01/16] dt-bindings: display: bridge: renesas,dsi: Document RZ/G3L

[Krzysztof Kozlowski <krzk@kernel.org>]

On Sat, Jul 04, 2026 at 10:34:11AM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> The RZ/G3L DSI IP is similar to the RZ/G2L but has different global PHY
> timings and also the PLLCLK is ungateble clock. Add the compatible
> string "renesas,r9a08g046-mipi-dsi" to handle these difference for the
> Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block.
> Document renesas,sysc-pwrrdy property to handle the power control.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../bindings/display/bridge/renesas,dsi.yaml      | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> index c20625b8425e..b114ac3b111a 100644
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> @@ -28,6 +28,7 @@ properties:
>            - const: renesas,r9a09g057-mipi-dsi
>  
>        - enum:
> +          - renesas,r9a08g046-mipi-dsi # RZ/G3L
>            - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
>  
>    reg:
> @@ -108,6 +109,20 @@ properties:
>    power-domains:
>      maxItems: 1
>  
> +  renesas,sysc-pwrrdy:
> +    description:
> +      The system controller PWRRDY indicates to the DSI region, if the power
> +      supply is ready. PWRRDY needs to be set during power-on before applying
> +      any other settings. It also needs to be set before powering off the DSI.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array

This feels a lot like a power domain. Please elaborate what is PWRRDY
and why power-on/off and power status within SoC (important!) is not
encoded as power domain.

Best regards,
Krzysztof