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Wed, 08 Jul 2026 05:11:05 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id 6685B2UD016208; Wed, 8 Jul 2026 05:11:02 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4f6u8kcs01-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Jul 2026 05:11:02 +0000 (GMT) Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 6685B2Bs016202; Wed, 8 Jul 2026 05:11:02 GMT Received: from hu-devc-hyd-u24-a.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.147.246.140]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 6685B1Jp016198 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Jul 2026 05:11:02 +0000 (GMT) Received: by hu-devc-hyd-u24-a.qualcomm.com (Postfix, from userid 429934) id DB83E2181C; Wed, 8 Jul 2026 10:41:00 +0530 (+0530) From: Mukesh Kumar Savaliya To: viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com, quic_jseerapu@quicinc.com, zhengxingda@iscas.ac.cn, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: krzysztof.kozlowski@oss.qualcomm.com, bartosz.golaszewski@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, Mukesh Kumar Savaliya Subject: [PATCH v8 4/4] i2c: qcom-geni: Support multi-owner controllers in GPI mode Date: Wed, 8 Jul 2026 10:40:10 +0530 Message-ID: <20260708051023.2872304-5-mukesh.savaliya@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708051023.2872304-1-mukesh.savaliya@oss.qualcomm.com> References: <20260708051023.2872304-1-mukesh.savaliya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-QCInternal: smtphost X-Authority-Analysis: v=2.4 cv=GJc41ONK c=1 sm=1 tr=0 ts=6a4ddbe9 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=r5MnBgDnrAiVjouRZIUA:9 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA4MDA0NiBTYWx0ZWRfXwcZNr2O+jNxw rFgR3hZuEqYqqhgwcapNdPyswZtVVy/Yarmms5vl9dbbUo07vG45RZu9xSHqWFoNh1g6ZhmyVR0 +klYyLIo5wyUYuki2FZ2jQ/6lyTB/5k= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA4MDA0NiBTYWx0ZWRfX/JqxDR/tQ3od zSu0e/TGlddtewu0Cuc+H4CNxUhkoCjJFdSIfaqDj6eRpCJW7ySSK5NWPFOdqwi80c0Q9tjaD55 Q7SfgPpmLFL23yW1cR8xTrHXHurbi8Jpv/E2CeSVReSZhQV4gaqwGzKjvOgE2qEpaKIVh5QzlL7 YO7iL+9J/GBS5f6s9PVEMvRlo5KvsrzBFE+lMxirg7aTABG49jEfSfP2rpPPzA3GPoVgdrEO5YI FoD0gZ1mpd29tPkOD62I73Z41IoI0fSSnZIocA0CIb0Kop5bMQ+C4D8eJOPg0SeZb8D1tVZiV0Q JO/FHdqxLCYDn9WDschuKgB9pB3z+MGHDzvCmZR/t5upwJmx51WraTbrgiBFF2ijzrmLY1cF6Ce YgNwpAUDFe2nN1ZF4V9k97Z21q+vZ9LFxfc81jxSUi3l0+PWZ3PcSCEXL5RjDqrz25qHQwNqa24 gAfvVFNHQTBTlkX/r9w== X-Proofpoint-ORIG-GUID: UxUcopPNPONFzT8JJBT9qpsUYotrqFAM X-Proofpoint-GUID: UxUcopPNPONFzT8JJBT9qpsUYotrqFAM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-07_06,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1011 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607080046 Some platforms use a QUP-based I2C controller in a configuration where the controller is shared with another system processor. In this setup the operating system must not assume exclusive ownership of the controller or its associated pins. Add support for enabling multi-owner operation when DeviceTree specifies qcom,qup-multi-owner. When enabled, mark the underlying serial engine as shared so the common GENI resource handling avoids selecting the "sleep" pinctrl state, which could disrupt transfers initiated by the other processor. For GPI mode transfers, request lock/unlock TRE sequencing from the GPI driver by setting a single lock_action selector per message, emitting lock before the first message and unlock after the last message (handling the single-message case as well). This serializes access to the shared controller without requiring message-position flags to be passed into the DMA engine layer. Signed-off-by: Mukesh Kumar Savaliya --- drivers/i2c/busses/i2c-qcom-geni.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 96dbf04138be..757c2c8eb207 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -832,6 +832,14 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i if (i < num - 1) peripheral.stretch = 1; + peripheral.lock_action = GPI_LOCK_NONE; + if (gi2c->se.multi_owner) { + if (i == 0) + peripheral.lock_action = GPI_LOCK_ACQUIRE; + else if (i == num - 1) + peripheral.lock_action = GPI_LOCK_RELEASE; + } + peripheral.addr = msgs[i].addr; if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) peripheral.multi_msg = false; @@ -1019,7 +1027,11 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) } if (fifo_disable) { - /* FIFO is disabled, so we can only use GPI DMA */ + /* + * FIFO is disabled, so only GPI DMA can be used. + * In multi-owner configurations, the SE may be shared between subsystems, + * with each subsystem owning a separate GPII. + */ gi2c->gpi_mode = true; ret = setup_gpi_dma(gi2c); if (ret) @@ -1028,6 +1040,11 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) dev_dbg(gi2c->se.dev, "Using GPI DMA mode for I2C\n"); } else { gi2c->gpi_mode = false; + + if (gi2c->se.multi_owner) + return dev_err_probe(gi2c->se.dev, -EINVAL, + "I2C sharing not supported in non GSI mode\n"); + tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ @@ -1098,6 +1115,11 @@ static int geni_i2c_probe(struct platform_device *pdev) gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ; } + if (of_property_read_bool(pdev->dev.of_node, "qcom,qup-multi-owner")) { + gi2c->se.multi_owner = true; + dev_dbg(&pdev->dev, "I2C controller is shared with another system processor\n"); + } + if (has_acpi_companion(dev)) ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); -- 2.43.0