Re: [PATCH v2] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The `interrupts`, `interrupt-map`, and `iommu-map` properties are incorrectly swapped between the `pcie0` and `pcie1` nodes.
- [High] Missing `msi-map` and `msi-map-mask` properties in both `pcie0` and `pcie1` controller nodes.
--

--- Patch [1]: [PATCH v2] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes ---
commit 3e6d0e6b1d707ae4bb730aa1670a7c5e1a2690b4
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes

Eliza supports two PCIe instances: one 8GT/s x1 (PCIe0) and one 8GT/s x2
(PCIe1). Add PCIe controller and PHY nodes for both instances, and update
the GCC clock references to use the newly added PHY nodes instead of
placeholder zeros.

> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
> index 977de44b816e4..7cfd242bc1929 100644
> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi
> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi

[ ... ]

> @@ -1786,6 +1786,367 @@ mmss_noc: interconnect@1780000 {
>  			#interconnect-cells = <2>;
>  		};
>  
> +		pcie0: pcie@1c00000 {
> +			device_type = "pci";
> +			compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550";

[ ... ]

> +			interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,

[ ... ]

> +			iommu-map = <0 &apps_smmu 0x1480 0x1>,
> +				    <0x100 &apps_smmu 0x1481 0x1>;

[Severity: High]
Are the interrupts, interrupt-map, and iommu-map properties swapped between
the pcie0 and pcie1 controllers?

Looking at both nodes, pcie0 claims GIC_SPI 376 and iommu-map 0x1480, while
pcie1 (at 0x1c08000) claims GIC_SPI 141 and iommu-map 0x1400. If these are
reversed, hardware interrupts and IOMMU Stream IDs will be cross-wired. 
This could cause DMA transactions to trigger SMMU context faults and route
endpoint interrupts to the wrong handler.

> +
> +			interrupt-map = <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 0 0 565 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 0 0 566 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 0 0 567 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			#interrupt-cells = <1>;

[Severity: High]
Should msi-map and msi-map-mask properties be included for this controller?

Without the msi-map property, the PCI core cannot map requester IDs to the
GIC ITS device IDs. This will force a fallback to the internal DesignWare
MSI controller, limiting the system to 32 standard MSIs and preventing
MSI-X support.

[ ... ]

> +		pcie1: pcie@1c08000 {
> +			device_type = "pci";
> +			compatible = "qcom,eliza-pcie", "qcom,pcie-sm8550";

[ ... ]

> +			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			#interrupt-cells = <1>;

[Severity: High]
Are msi-map and msi-map-mask properties also missing here for pcie1?

Similar to pcie0, missing these properties will break MSI-X support for
devices connected to this controller.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260708-eliza_dt-v2-1-e6281da26408@oss.qualcomm.com?part=1