Re: [PATCH 1/2] arm64: dts: mediatek: alias all enabled serial ports on Genio boards

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Incomplete fix: mt8390-tungsten-smarc.dtsi leaves multiple enabled UARTs without aliases, remaining vulnerable to the console probe-deferral race condition.
--

--- Patch [1]: [PATCH 1/2] arm64: dts: mediatek: alias all enabled serial ports on Genio boards ---
commit e24717bbabf68ad0b7411bc7cc53b4c950007efe
Author: Carlo Caione <ccaione@baylibre.com>

arm64: dts: mediatek: alias all enabled serial ports on Genio boards

Only serial0 is aliased, so the remaining enabled uarts get first-free
line numbers. When the console uart defers on its clocks, another uart
can win line 0: console=ttyS0 then ends up on the wrong connector and
the boot looks like a hang on the serial console, depending on probe
order. Alias every enabled uart so line numbers are stable.

[ ... ]

> diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> index b0c97930a0e6c..26e24431d467d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> @@ -33,6 +33,8 @@ aliases {
>  		mmc0 = &mmc0;
>  		mmc1 = &mmc1;
>  		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
>  	};

[Severity: High]
This isn't a bug introduced by this patch, but does this incomplete fix
leave other MT8390 boards vulnerable to the console probe-deferral race?

Looking at the aliases node in
arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi:

	aliases {
		dsi0 = &disp_dsi0;
		ethernet0 = &eth;
[ ... ]
		rtc1 = &mt6359rtc;
		serial0 = &uart0;
	};

It fails to define serial1 = &uart1; and serial2 = &uart2; for the enabled
secondary UARTs. If the primary console UART (uart0) defers during probe
due to clock dependencies, can a secondary enabled UART (uart1 or uart2)
successfully probe before uart0 is ready and take the first available
unaliased line (ttyS0)?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260708-ccaione-genio-serial-aliases-v1-0-bf22229e9383@baylibre.com?part=1