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Wed, 08 Jul 2026 09:59:38 -0700 (PDT) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493e0faed92sm141201035e9.9.2026.07.08.09.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 09:59:37 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com Subject: [PATCH v8 0/4] arm64: dts: nuvoton: add NPCM845 SoC and EVB support Date: Wed, 8 Jul 2026 19:59:25 +0300 Message-Id: <20260708165929.2233934-1-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This series fixes the remaining timer binding issue and adds device tree=0D support for peripherals on the Nuvoton NPCM845 SoC and its Evaluation=0D Board (EVB).=0D =0D The first patch drops the undocumented timer0 clock-names property.=0D The second patch reorders timer0 and PECI so the APB child nodes stay in=0D ascending unit-address order.=0D The third patch introduces peripheral nodes for Ethernet, MMC, SPI, USB,=0D RNG, ADC, PWM-FAN, I2C, and OP-TEE firmware in the NPCM845 SoC device=0D tree.=0D The fourth patch enables these peripherals for the NPCM845-EVB, adding=0D MDIO nodes, reserved memory, aliases, and board-specific configurations=0D such as PHY modes and SPI flash partitions.=0D =0D The NPCM8XX device tree was tested on NPCM845 evaluation board.=0D =0D Addressed comments from:=0D - sashiko-bot=0D =0D Changes since version 7:=0D - modify timer place.=0D - add PSPI to commit message.=0D =0D Changes since version 6:=0D - remove IPMI i2C device.=0D - Add FIX enable property.=0D - Keep patches 1-3 unchanged.=0D =0D Changes since version 5:=0D - Add no-map to the tip_reserved firmware memory region.=0D - Drop the unsupported snps,eee-force-disable property from gmac1.= =0D - Rework the FIU0 boot flash layout into nested fixed-partitions=0D under the bmc container.=0D - Keep patches 1-3 unchanged.=0D =0D Changes since version 4:=0D - Split the timer0 clock-names cleanup into a separate first patch.= =0D - Remove nuvoton,sysgcr from udc8 and udc9.=0D - Rename apb: bus@f0000000 back to apb.=0D - Rename spix-mode to nuvoton,spix-mode.=0D - Keep cooling-levels as 32-bit cells while encoding fan-tach-ch=0D as /bits/ 8.=0D =0D Changes since version 3:=0D - reomve tmp100.=0D =0D Changes since version 2:=0D - Fix dts warning=0D - Arrange node order by ascending unit address.=0D =0D Changes since version 1:=0D - Fix commit message=0D - Fix dtbs_check warnings.=0D Tomer Maimon (4): arm64: dts: nuvoton: npcm845: Drop redundant timer clock-names arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes arm64: dts: nuvoton: npcm845: Add peripheral nodes arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 721 +++++++++++++++++- .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 404 ++++++++++ .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 7 + 3 files changed, 1115 insertions(+), 17 deletions(-) --=20 2.34.1