From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29963348C48 for ; Thu, 9 Jul 2026 13:42:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783604551; cv=none; b=Pf3AwrK6oxTk4FXORbDkIVK/0XpRnzY58IhA89ccVy0lfsrJux4qpss5blAZi/B1jLrImJ3RvwX4gqVw59xM3UJeAFpkpiEP16x08Df5EynPwFAX/622wEr1DjK/OIT4MqxPWYckEO0XJQm29FZ5ZuPkfrnN8LtUvpYqNnPqqJw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783604551; c=relaxed/simple; bh=UNUL9Mr0l2L8Lqs+wHPrdAEPNY6fCsW9k5nh51lE3yE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CHK0wbqg8rwKWhviTeAk58iFzhGnXAo7cNUai0kuhys+/VSjKBQLgfO5vYD0qZTf8lMTk6gsfmUQ+BOGdMtDxbyxLUuF6vTSHYQl3febkfxwaVCQtH0xiXnWvs9Hhpq9Cc/vRBTHFHnh9Y9In27aBBuZ6K0oWSFkRVMiNZ3x0uU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Cb3xu7JX; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=aBeTeI5s; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Cb3xu7JX"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="aBeTeI5s" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 669BNMHZ1667680 for ; Thu, 9 Jul 2026 13:42:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 6VtT1Xc7mzYmEVXSOrS2xHmSXZj1i0soFFiiNBvav0A=; b=Cb3xu7JX8tVYXDz/ Pfq8iEK9Mr6fyVCChi/NvXNYuXACCqfVCdAx9URXi54XiJ/tCuoAsPGd3yPRNNck LITR0o/QcIFp4VJjOBTwp9tpkg1ptbu/dVKOl9oVVxl0e9T3E5vRCuhHrp91wauT tLrzRtdTHhTCK0m92PRHdn+yhKplT1oStoXEbAjJQ0X5k7EAOPttd5u0bG0WdwTX TknNHPHYlYzNDoxbcb8DHookkX7ueYKqSugyi4hPKZ3YOUB3DkFrnduuMnVsJUOj O8Aq3WelgYChTROdHW/kSCzb5GGFFpUITElcA6JWhqIVNTwTfhV+pq73tEie9vkf H7VBwg== Received: from mail-vs1-f72.google.com (mail-vs1-f72.google.com [209.85.217.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f9ug6m1gu-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 09 Jul 2026 13:42:29 +0000 (GMT) Received: by mail-vs1-f72.google.com with SMTP id ada2fe7eead31-744dc532943so762553137.3 for ; Thu, 09 Jul 2026 06:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1783604548; x=1784209348; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=6VtT1Xc7mzYmEVXSOrS2xHmSXZj1i0soFFiiNBvav0A=; b=aBeTeI5svTNwhbZ5G5FWrrADE7Y9pG4oYWFNpniH07HgROTHg7ZI8GwcxoNOW409Za SnGNz8vhaZVD3yGUK94pcVaPyvEaNdMoqmNBhnRAdqI3HcGOit6fDXHU46QI/y8VGY7s wkjs4+h8CwgtHZo1goJCutBsnqIgOTJPHiRrWnn9wI5EaMUU3DCp85/lweYTETJ+kTrC 3q67Bj3f0VZM4v3yXVUUq1i954FWY9Eb7Pj3TQsOp9k589981y5CNRy0j90q7dV+gocA go9TWnqiTTUYYtgBrOWTY5JZ+GIQBet9vnFemYnaIIZPP1W1Xxq2vw/DZw6g1yw2sKcJ ZcfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783604548; x=1784209348; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=6VtT1Xc7mzYmEVXSOrS2xHmSXZj1i0soFFiiNBvav0A=; b=kc9mLYtxIwKUq4mhlYYSAFRBya7poewAz2vVK62/bPMuznb27QeAm41njonC4duvzs ft3DsoQXueO5s1q4QF/Y+CFoAegJL+pyqQTauqfTr3gzr+Kujg9575eyr42kO+c+074j 4J8yJOHk0rT0Qk9VrS+Xli3/99S/xkPt48DbvZXSqX8Cojd/znnGUXy56DbiqIXMFcCK 0OGzyduYKJ1YCsv1hQVj2bhwaXLjvupPktZh+1X3NctvKCxPdAVU4dIC+oZM7TT3cGZe Yw9d5K1l/VGFlG9QSgoJl3sxwjU1uZBWTzANcxSUKYl1RF8IRue7vM0sLuQKqyvdn4yP 5Cog== X-Forwarded-Encrypted: i=1; AHgh+RrCZENAUm8jZKLBDmOQPYeLdP+GMrKl9ho+CkdpLFQEQCJpysJfPC+mvvFzvd77FEozkIslgIjNaYlM@vger.kernel.org X-Gm-Message-State: AOJu0YzcZ/mkIvkKa4eNC3nV7A7VyeargUinK8/mnFKtLfzedLnwBcDZ i94Bvzmh00LuqfSTjgkiqkIDXQhQEvHkBjUmuExDtiG68muqxCKIqTLPvSXS99Md12se3aEjWlY eRYQ3+Y1t0vaHXrKb2PtHmOPGua968E8Pu5RunxEqiWQUtzM/SXAx3xUN1MgG0DQesMg5rggR X-Gm-Gg: AfdE7ckeyvzqQKI3c22Va4lVp4YJUCCt0AP6oKiK1LvNbDg07MdnVs+u+hS+ABOuyfH 857w/4jLcSzH1S+8Rh4FgvYhZ9NYYn9DnViKZUsA9aYFOmrk7XTtEWrBXGoyBF7vJKJEtQLoGlh bYb0VwptdMNsWwebJqlwT+sUC+QyR0IpAqkzr6rjCeTdtpsrelFCMcez8LlX/LxFspbtUmWYWYx omu1wCPaOBxARm+27ZYsMh7yF+j2rC9RLbIg8OYKoXKfdVtZGuo2J1K08CcMGmrH9mcJ4YlnN4G L5LlB4sULBQLgPIyzuaWLRd4bb2Ab/QCS1QFVfkXle0VAKqJMaJvEcHWTyrZKtZmcTDE9O3q3UZ xKEch+Zu/oRpXn0lRCE44pkTCaji/i6au0+GfT6hdbkZETApkHthh7lWWhKp5LAgdrCS9XXv4eM GiYPOsprYOskwxOMuC+pR/l7vg X-Received: by 2002:a05:6102:54a8:b0:643:80f1:350a with SMTP id ada2fe7eead31-744dfd09748mr5256027137.2.1783604548316; Thu, 09 Jul 2026 06:42:28 -0700 (PDT) X-Received: by 2002:a05:6102:54a8:b0:643:80f1:350a with SMTP id ada2fe7eead31-744dfd09748mr5255996137.2.1783604547783; Thu, 09 Jul 2026 06:42:27 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-39c849186e1sm3345151fa.9.2026.07.09.06.42.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2026 06:42:26 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 09 Jul 2026 16:42:02 +0300 Subject: [PATCH v7 11/18] media: iris: Add framework support for AR50_LITE video core Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260709-iris-ar50lt-v7-11-76af9dd4d1f6@oss.qualcomm.com> References: <20260709-iris-ar50lt-v7-0-76af9dd4d1f6@oss.qualcomm.com> In-Reply-To: <20260709-iris-ar50lt-v7-0-76af9dd4d1f6@oss.qualcomm.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10669; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=vbLao7R78n3Cd+uUYw/mexaoZuBaorBehVeJUdtqoNk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqT6UlP5zTuDVdKJZKipOw65lNQcaK0CNw54aRp A0EBikBlwWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCak+lJQAKCRCLPIo+Aiko 1ZshB/0df+hlmxhoJO7xq35Cdsljj6YXv2z3HZqvvAcKff0k9io4cl6eGJA3qi970+21Nm0J4BJ Lz7IWAlee2oyycomB9fNfb0EOQPCW+Z8a4fhGL80nBM19x9NqyWgTbUgZlmBs5+7mNfKNV5JHqC +s799XuH0U9f5EX07j0Ia7ExyyhjXoOTrDcR8cIEuHf9GcVLTegOiAN9OORLioupOSeKF0E8BuV dS/8cPfOWDVB0tZRnmVikN5UoU1kh8F7M62qj/R400DrbpyLWF9EB7dPkpliDb0ZmXZbdhKdFEx QGNQ4vaITJa/2LtvkHLQ/uoigqVohkiLcBywSRjipXrr+jpU X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA5MDEzNCBTYWx0ZWRfX7WCAsAZfxnKc H/2EpsOQUxX62YnLs8lQdmkPCCUOQmcFQcXItJc6SlMe0kJiZl14aH3L5wVW+rQu0ghm5nq8rrT +QsDwwA4xokU2F3QvDpyIwqFgBwlk94= X-Proofpoint-GUID: zNCoRb0Ec4JIXNsAnmFiIb7hIq08Ud2U X-Authority-Analysis: v=2.4 cv=cL3QdFeN c=1 sm=1 tr=0 ts=6a4fa545 cx=c_pps a=DUEm7b3gzWu7BqY5nP7+9g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=oth-URKmseDdlDMfR28A:9 a=QEXdDO2ut3YA:10 a=-aSRE8QhW-JAV6biHavz:22 X-Proofpoint-ORIG-GUID: zNCoRb0Ec4JIXNsAnmFiIb7hIq08Ud2U X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA5MDEzNCBTYWx0ZWRfX3rmYoy6H/9HI gdISWUKViqjc9AUKcvQFaXUYGkR8wv2oueJl+HQfcbLv0beClfCMoUTDNR6PYK4Q3iVY3Pnfugo 9RloV1+dNDcZ8X3/BtoQWnCitg1IZqAkh+vQTkaHYpzAGsF4Umk1TwY6sOJvjNyYh0aMwFAFX3e 942DAGsfvbk+EspaBUAKc83/a2pKE8mc/Tdz/F/+XQBNnqEQOtTzMARslR7Tq9atQE0rCrFUAPm h2t2gNMrVIKuBD0oGXCR/ezoEo9rqNE45z0OW0PJBk+/22byQfmws+0fI3NsktrVqV5RkHiP9SJ Q9DgAtqU0a9wetKyR0HIs1/VHX7kd46j/mg4A5RsLtsaMXDlu8ueu7djJe2hmaFJtjQ1q4o96WP VtKOndCfpEJTXzuIGGn86APhy+h+L4rGl7sjIvcUD1q+Eu1rLG3qw6R8uAZQbFpcwgNOp1GJLDE X6qTn4LDrKPOQD7d2EA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-09_02,2026-07-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607090134 From: Dikshita Agarwal Add power sequence for ar5lt core. Add register handling for ar50lt by hooking up vpu op with ar50lt specific implemtation or resue from earlier generation wherever feasible. Signed-off-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 + drivers/media/platform/qcom/iris/iris_vpu2.c | 28 +---- drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 130 +++++++++++++++++++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 29 ++++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 + 6 files changed, 164 insertions(+), 28 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 48e415cbc439..f1b204b95694 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -26,6 +26,7 @@ qcom-iris-objs += iris_buffer.o \ iris_vpu2.o \ iris_vpu3x.o \ iris_vpu4x.o \ + iris_vpu_ar50lt.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index accc1627defd..6a189489369f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -74,6 +74,7 @@ enum platform_clk_type { IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, IRIS_APV_HW_CLK, + IRIS_THROTTLE_CLK, }; struct platform_clk_data { @@ -315,6 +316,7 @@ struct iris_platform_data { u32 tz_cp_config_data_size; u32 num_vpp_pipe; bool no_aon; + bool no_rpmh; u32 wd_intr_mask; u32 icc_ib_multiplier; u32 max_session_count; diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c index dd2eeae0d9eb..5419a5096b00 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -12,38 +12,12 @@ #include "iris_vpu_register_defines.h" -static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) -{ - struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps; - struct v4l2_format *inp_f = inst->fmt_src; - u32 mbs_per_second, mbpf, height, width; - unsigned long vpp_freq, vsp_freq; - u32 fps = inst->frame_rate; - - width = max(inp_f->fmt.pix_mp.width, inst->crop.width); - height = max(inp_f->fmt.pix_mp.height, inst->crop.height); - - mbpf = NUM_MBS_PER_FRAME(height, width); - mbs_per_second = mbpf * fps; - - vpp_freq = mbs_per_second * caps->mb_cycles_vpp; - - /* 21 / 20 is overhead factor */ - vpp_freq += vpp_freq / 20; - vsp_freq = mbs_per_second * caps->mb_cycles_vsp; - - /* 10 / 7 is overhead factor */ - vsp_freq += ((fps * data_size * 8) * 10) / 7; - - return max(vpp_freq, vsp_freq); -} - const struct vpu_ops iris_vpu2_ops = { .power_off_hw = iris_vpu_power_off_hw, .power_on_hw = iris_vpu_power_on_hw, .power_off_controller = iris_vpu_power_off_controller, .power_on_controller = iris_vpu_power_on_controller, - .calc_freq = iris_vpu2_calc_freq, + .calc_freq = iris_vpu2_calculate_frequency, .set_hwmode = iris_vpu_set_hwmode, .set_preset_registers = iris_vpu_set_preset_registers, .interrupt_init = iris_vpu_interrupt_init, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c new file mode 100644 index 000000000000..e084a5b49f2e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "iris_instance.h" +#include "iris_vpu_common.h" + +#include "iris_vpu_register_defines.h" + +#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT BIT(3) + +#define WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT 0xb0080 + +#define CPU_CS_VCICMD 0xa0020 +#define CPU_CS_VCICMD_ARP_OFF 0x1 + +static void iris_vpu_ar50lt_set_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT); +} + +static void iris_vpu_ar50lt_interrupt_init(struct iris_core *core) +{ + writel(WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT, core->reg_base + WRAPPER_INTR_MASK); +} + +static void iris_vpu_ar50lt_disable_arp(struct iris_core *core) +{ + writel(CPU_CS_VCICMD_ARP_OFF, core->reg_base + CPU_CS_VCICMD); +} + +static int iris_vpu_ar50lt_power_off_controller(struct iris_core *core) +{ + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + + return 0; +} + +static void iris_vpu_ar50lt_power_off_hw(struct iris_core *core) +{ + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); + iris_disable_unprepare_clock(core, IRIS_THROTTLE_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); +} + +static int iris_vpu_ar50lt_power_on_controller(struct iris_core *core) +{ + int ret; + + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + if (ret) + return ret; + + ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK); + if (ret) + goto err_disable_power; + + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + if (ret && ret != -ENOENT) + goto err_disable_ctrl_clock; + + ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK); + if (ret) + goto err_disable_axi_clock; + + return 0; + +err_disable_axi_clock: + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); +err_disable_ctrl_clock: + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); + + return ret; +} + +static int iris_vpu_ar50lt_power_on_hw(struct iris_core *core) +{ + int ret; + + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto err_disable_power; + + ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + if (ret) + goto err_disable_hw_clock; + + ret = iris_prepare_enable_clock(core, IRIS_THROTTLE_CLK); + if (ret) + goto err_disable_hw_ahb_clock; + + return 0; + +err_disable_hw_ahb_clock: + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + + return ret; +} + +const struct vpu_ops iris_vpu_ar50lt_ops = { + .power_off_hw = iris_vpu_ar50lt_power_off_hw, + .power_on_hw = iris_vpu_ar50lt_power_on_hw, + .power_off_controller = iris_vpu_ar50lt_power_off_controller, + .power_on_controller = iris_vpu_ar50lt_power_on_controller, + .calc_freq = iris_vpu2_calculate_frequency, + .set_hwmode = iris_vpu_set_hwmode, + .set_preset_registers = iris_vpu_ar50lt_set_preset_registers, + .interrupt_init = iris_vpu_ar50lt_interrupt_init, + .disable_arp = iris_vpu_ar50lt_disable_arp, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index 41498f94480e..d64e7745a63d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -97,7 +97,8 @@ int iris_vpu_boot_firmware(struct iris_core *core) } writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN); - writel(0x0, core->reg_base + CPU_CS_X2RPMH); + if (!core->iris_platform_data->no_rpmh) + writel(0x0, core->reg_base + CPU_CS_X2RPMH); return 0; } @@ -422,6 +423,32 @@ void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core) writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0); } +u64 iris_vpu2_calculate_frequency(struct iris_inst *inst, size_t data_size) +{ + struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps; + struct v4l2_format *inp_f = inst->fmt_src; + u32 mbs_per_second, mbpf, height, width; + unsigned long vpp_freq, vsp_freq; + u32 fps = inst->frame_rate; + + width = max(inp_f->fmt.pix_mp.width, inst->crop.width); + height = max(inp_f->fmt.pix_mp.height, inst->crop.height); + + mbpf = NUM_MBS_PER_FRAME(height, width); + mbs_per_second = mbpf * fps; + + vpp_freq = mbs_per_second * caps->mb_cycles_vpp; + + /* 21 / 20 is overhead factor */ + vpp_freq += vpp_freq / 20; + vsp_freq = mbs_per_second * caps->mb_cycles_vsp; + + /* 10 / 7 is overhead factor */ + vsp_freq += ((fps * data_size * 8) * 10) / 7; + + return max(vpp_freq, vsp_freq); +} + u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size) { struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index 71d96921ed37..a62b6184bde7 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; extern const struct vpu_ops iris_vpu4x_ops; +extern const struct vpu_ops iris_vpu_ar50lt_ops; struct vpu_ops { void (*power_off_hw)(struct iris_core *core); @@ -40,6 +41,7 @@ int iris_vpu_power_on(struct iris_core *core); int iris_vpu_power_off_controller(struct iris_core *core); void iris_vpu_power_off_hw(struct iris_core *core); void iris_vpu_power_off(struct iris_core *core); +u64 iris_vpu2_calculate_frequency(struct iris_inst *inst, size_t data_size); int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core); int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core); void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core); -- 2.47.3