From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA015329E6A; Thu, 9 Jul 2026 13:42:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783604580; cv=none; b=VzwRG456UK5YD6N1yQsYthdbFxsIzik4OKZ5SDi+PBtC9blHfRWCqi0Yuhwyk+LHRFb73eT01I+hXk0S7bnLGG3/ssX7VsJ0L9v8FB0sRS8sQiaOhmuxGGpUVvB9Bhr26KTdEbm3VHKv+vU+hwAGBGGijcnPnE7cZ2zcOe0wO8I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783604580; c=relaxed/simple; bh=XVmQ+2qFrG9vLkAnDq/06nyA/RqY1ZBMtY7S+LPpWaU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k25Kt3uz+DZapXHZn7bF2tB4sar24MSqv4weTmIcpYf0e6C70qa8RlyrkM8XeaL3EkOc6LZJmh4WQ16WpYeq8b8JmQo2B2lxR9UuhlMv3fSClnoDaN57UibXvhpwGSisfqpV+e5AE+Dny4yA79tr2xTxs7nWvZM23Cq2gba8da0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=oVImF296; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="oVImF296" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1783604577; bh=XVmQ+2qFrG9vLkAnDq/06nyA/RqY1ZBMtY7S+LPpWaU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oVImF296B76BMDIxAVQ4pJJDt53hrkqTylVfIQHhdJBGG+JOXoiTpkQ4HlShRIGBy +99eWiwyga17EpieTxMoalweIwqEbJVcpqzSojMerBq6uvv6DIsyQqdkwJVjIpiqh8 oLUw/wQASVLKfyiPockzv9G+0EFZTEbDXiHZfdG0j8vh4nTrWYzWudnuvmmjIAAU3O 4LJlUXMo2m+Lz7tGKUuwNJROCvkVU/uTdMRYbZW/GKpSHLyqfctv/RpUUFMHkKXvwZ iPwNuuVadwtrd6QH9clL+5fLdrt8L/Jw6QW6wS/OOV+9GM2Y/OTN7tLo+VKBJoYFf6 WARllp/BN5u+Q== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5FDEC17E0D33; Thu, 09 Jul 2026 15:42:56 +0200 (CEST) From: Louis-Alexis Eyraud Date: Thu, 09 Jul 2026 15:42:41 +0200 Subject: [PATCH v2 01/18] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260709-mt8189-clocks-system-base-v2-1-2926da3db6cf@collabora.com> References: <20260709-mt8189-clocks-system-base-v2-0-2926da3db6cf@collabora.com> In-Reply-To: <20260709-mt8189-clocks-system-base-v2-0-2926da3db6cf@collabora.com> To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Philipp Zabel , Edward-JW Yang , Richard Cochran Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783604575; l=1522; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=XVmQ+2qFrG9vLkAnDq/06nyA/RqY1ZBMtY7S+LPpWaU=; b=TZqFueTbwacWEBBWgedvAqgyOZaJQfOAUdmA5xfp9iOqcMd940T7OGr1evceMtt33cretyDKu QlKQisUifu6CxS+l3ECkxIGw9tu9v+NFL9kTP3G6dhd2GzcKQ+ZPKtq X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Both MT8186 clock controllers dt-bindings (clock and sys-clock) document the '#clock-cells' property but do not enforce it as required property. As clock provider nodes should define this property in devicetrees, add it to the required property list in both its dt-bindings files. Signed-off-by: Louis-Alexis Eyraud --- Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml | 1 + Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml index f4e58bfa504f..539149c945d0 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml @@ -44,6 +44,7 @@ properties: required: - compatible - reg + - '#clock-cells' additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml index 1c446fbc5108..f8acc02cafee 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -45,6 +45,7 @@ properties: required: - compatible - reg + - '#clock-cells' additionalProperties: false -- 2.55.0