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However the parent clock of clk_in1 can still be gated, disabled, or (re-)enabled after FPGA programming (typical FPGA Manager flows, CCF-managed parents, PLL fabric power sequencing). Add a 10 us delay in each output clock's .enable() hook so consumers wait for reference settling before first access. Signed-off-by: Shubhrajyoti Datta --- (no changes since v1) drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 137 ++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index ffc78c90bee6..5470a717fccc 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -107,6 +108,7 @@ #define VER_WZRD_O_MAX 511 #define WZRD_MIN_ERR 20000 #define WZRD_FRAC_POINTS 1000 +#define WZRD_ENABLE_DELAY_US 10 /* Get the mask from width */ #define div_mask(width) ((1 << (width)) - 1) @@ -697,6 +699,13 @@ static int clk_wzrd_ver_determine_rate_all(struct clk_hw *hw, return 0; } +static int clk_wzrd_enable(struct clk_hw *hw) +{ + /* Allow the output clock to settle after enable */ + udelay(WZRD_ENABLE_DELAY_US); + return 0; +} + static const struct clk_ops clk_wzrd_ver_divider_ops = { .determine_rate = clk_wzrd_determine_rate, .set_rate = clk_wzrd_ver_dynamic_reconfig, @@ -790,6 +799,85 @@ static const struct clk_ops clk_wzrd_clk_divider_ops_f = { .recalc_rate = clk_wzrd_recalc_ratef, }; +static unsigned long +clk_wzrd_static_factor_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); + unsigned long long rate; + + rate = (unsigned long long)parent_rate * fix->mult; + do_div(rate, fix->div); + return (unsigned long)rate; +} + +static int clk_wzrd_static_factor_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + unsigned long best_parent; + + best_parent = (req->rate / fix->mult) * fix->div; + req->best_parent_rate = + clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); + } + + req->rate = (req->best_parent_rate / fix->div) * fix->mult; + + return 0; +} + +static int clk_wzrd_static_factor_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + return 0; +} + +static const struct clk_ops clk_wzrd_static_fixed_factor_ops = { + .enable = clk_wzrd_enable, + .determine_rate = clk_wzrd_static_factor_determine_rate, + .set_rate = clk_wzrd_static_factor_set_rate, + .recalc_rate = clk_wzrd_static_factor_recalc_rate, +}; + +static struct clk_hw * +clk_wzrd_devm_register_static_fixed_factor(struct device *dev, + const char *name, + const struct clk_parent_data *parent_data, + unsigned long flags, + unsigned int mult, + unsigned int div) +{ + struct clk_init_data init = {}; + struct clk_fixed_factor *fix; + struct clk_hw *hw; + int ret; + + fix = devm_kzalloc(dev, sizeof(*fix), GFP_KERNEL); + if (!fix) + return ERR_PTR(-ENOMEM); + + fix->mult = mult; + fix->div = div; + + init.name = name; + init.ops = &clk_wzrd_static_fixed_factor_ops; + init.flags = flags; + init.parent_data = parent_data; + init.num_parents = 1; + + fix->hw.init = &init; + + hw = &fix->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + return hw; +} + static struct clk_hw *clk_wzrd_register_divf(struct device *dev, const char *name, const char *parent_name, @@ -1154,9 +1242,11 @@ static int clk_wzrd_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct clk_wzrd *clk_wzrd; + const char *clk_name; unsigned long rate; + struct clk_hw *hw; int nr_outputs; - int ret; + int ret, i; ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); if (ret || nr_outputs > WZRD_NUM_OUTPUTS) @@ -1224,6 +1314,51 @@ static int clk_wzrd_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "unable to register clock notifier\n"); } + } else { + u32 mul_div[WZRD_NUM_OUTPUTS * 2]; + const struct clk_parent_data parent_data = { .fw_name = "clk_in1" }; + int num_elems = nr_outputs * 2; + + /* + * xlnx,clk-mul-div is a uint32-matrix of pairs; + * FDT encodes it as a flat u32 array so we can read it directly. + */ + ret = of_property_read_u32_array(np, "xlnx,clk-mul-div", + mul_div, num_elems); + if (ret) { + dev_err(&pdev->dev, "xlnx,clk-mul-div missing or invalid\n"); + return ret; + } + + for (i = 0; i < nr_outputs; i++) { + u32 mul = mul_div[2 * i]; + u32 div = mul_div[2 * i + 1]; + + if (!mul || !div) + return dev_err_probe(&pdev->dev, -EINVAL, + "invalid mul/div for clkout%d\n", i); + + clk_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "%s_out%d", dev_name(&pdev->dev), i); + if (!clk_name) + return -ENOMEM; + + hw = clk_wzrd_devm_register_static_fixed_factor(&pdev->dev, clk_name, + &parent_data, + CLK_SET_RATE_PARENT, + mul, div); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_wzrd->clk_data.hws[i] = hw; + } + + clk_wzrd->clk_data.num = nr_outputs; + + ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + &clk_wzrd->clk_data); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "unable to register clock provider\n"); } return 0; -- 2.34.1