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From: sashiko-bot@kernel.org
To: "Changhuang Liang" <changhuang.liang@starfivetech.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v1 03/11] spi: dw: update SPI_CTRLR0 register
Date: Thu, 09 Jul 2026 14:00:14 +0000	[thread overview]
Message-ID: <20260709140014.A1D0F1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260709055204.138168-4-changhuang.liang@starfivetech.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The newly introduced `enh_cfg` parameter in `dw_spi_update_config()` is never populated or passed by any caller, rendering the enhanced mode configuration logic effectively dead code.
--

--- Patch [3]: [PATCH v1 03/11] spi: dw: update SPI_CTRLR0 register ---
commit b571b86cd59a7cddd50fbc1933264b4589cd6f16
Author: Sudip Mukherjee <sudip.mukherjee@sifive.com>

spi: dw: update SPI_CTRLR0 register

This commit updates the SPI DesignWare driver to configure the SPI_CTRLR0
register for enhanced mode transfers. It introduces a new dw_spi_enh_cfg
structure and passes it to dw_spi_update_config() to set up instruction 
lengths, address lengths, and wait cycles.

> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> index 8d4ad4035d7c9..6befe47929b4c 100644
> --- a/drivers/spi/spi-dw-core.c
> +++ b/drivers/spi/spi-dw-core.c
[ ... ]
> @@ -451,7 +460,7 @@ static int dw_spi_transfer_one(struct spi_controller *ctlr,
>  
>  	dw_spi_enable_chip(dws, 0);
>  
> -	dw_spi_update_config(dws, spi, &cfg);
> +	dw_spi_update_config(dws, spi, &cfg, NULL);

[Severity: Medium]
Is this intended to always be NULL here? By passing NULL unconditionally, 
the new enhanced configuration block in dw_spi_update_config() will never 
execute for this path.

[ ... ]
> @@ -718,7 +727,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
>  
>  	dw_spi_enable_chip(dws, 0);
>  
> -	dw_spi_update_config(dws, mem->spi, &cfg);
> +	dw_spi_update_config(dws, mem->spi, &cfg, NULL);

[Severity: Medium]
Similarly in dw_spi_exec_mem_op(), the enh_cfg parameter is also 
unconditionally passed as NULL. Is there a missing piece that was supposed 
to extract the enhanced mode configurations from the memory operation and 
pass them along? 

Since all current callers provide NULL, the newly added SPI_CTRLR0 register 
update logic inside dw_spi_update_config() appears to be permanently 
unreachable.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260709055204.138168-1-changhuang.liang@starfivetech.com?part=3

  reply	other threads:[~2026-07-09 14:00 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-09  5:51 [PATCH v1 00/11] Add support for StarFive JHB100 SFC Changhuang Liang
2026-07-09  5:51 ` [PATCH v1 01/11] spi: dw: Introduce spi_frf and STD_SPI Changhuang Liang
2026-07-09  5:51 ` [PATCH v1 02/11] spi: dw: update NDF while using enhanced spi mode Changhuang Liang
2026-07-09 13:50   ` sashiko-bot
2026-07-09  5:51 ` [PATCH v1 03/11] spi: dw: update SPI_CTRLR0 register Changhuang Liang
2026-07-09 14:00   ` sashiko-bot [this message]
2026-07-09  5:51 ` [PATCH v1 04/11] spi: dw: add check for support of enhanced spi Changhuang Liang
2026-07-09 14:13   ` sashiko-bot
2026-07-09  5:51 ` [PATCH v1 05/11] spi: dw: Introduce enhanced single/dual/quad/octal spi Changhuang Liang
2026-07-09 14:23   ` sashiko-bot
2026-07-09  5:51 ` [PATCH v1 06/11] spi: dw: send cmd and addr to start the spi transfer Changhuang Liang
2026-07-09 14:37   ` sashiko-bot
2026-07-09  5:52 ` [PATCH v1 07/11] spi: dw: use irq handler for enhanced spi Changhuang Liang
2026-07-09 14:50   ` sashiko-bot
2026-07-09  5:52 ` [PATCH v1 08/11] spi: dw: adjust size of mem_op Changhuang Liang
2026-07-09 15:08   ` sashiko-bot
2026-07-09  5:52 ` [PATCH v1 09/11] spi: dw: detect enhanced spi mode Changhuang Liang
2026-07-09 15:20   ` sashiko-bot
2026-07-09  5:52 ` [PATCH v1 10/11] spi: dt-bindings: snps,dw-apb-ssi: Add starfive,jhb100-sfc Changhuang Liang
2026-07-09 17:55   ` Conor Dooley
2026-07-09  5:52 ` [PATCH v1 11/11] spi: dw: Add support for StarFive JHB100 SoC SFC Changhuang Liang
2026-07-09 15:34   ` sashiko-bot

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