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Miller" , Herbert Xu , Jonathan Corbet , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Rob Herring , Saravanakrishnan Krishnamoorthy , Shuah Khan Cc: Alexandre Ghiti , devicetree@vger.kernel.org, Joel Wittenauer , linux-api@vger.kernel.org, linux-crypto@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Shuah Khan , Thi Nguyen Subject: [PATCH v2 01/19] dt-bindings: crypto: add Rambus CryptoManager Hub Date: Thu, 9 Jul 2026 13:30:19 -0700 Message-ID: <20260709203037.1884436-2-skrishnamoorthy@rambus.com> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260709203037.1884436-1-skrishnamoorthy@rambus.com> References: <20260709203037.1884436-1-skrishnamoorthy@rambus.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|BY5PR04MB6616:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: a557af88-fc53-4c7d-a0d7-08deddf90985 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|7416014|23010399003|3023799007|921020|22082099003|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: /f1U9Cql6gOhWRK7hdAtYDoxuIjGUmxTolwYtxGFMA6OIoK7OQeOejkhWqOPCeUrZb335QGTPLzUBzWgZq7JBl2MYZrLDBeQ8K4m6ZEx1gKultDLLw/2B4DSIsHSTFy5uxrszPQQOh+u9RZp1HHzhqH+nLvvyfExQg/DcUISkDYhetA+7Yp75q0uC57EZ5hjVc1wnXmaKf1YOFw/ZAHCzUQUTmnC7gsPHpyNdJVrcAYs0X2CQS0JfX9JePFzZTfR76fBuOUWReffchi2vAgLDAsxLO91ov0P4NgY7VKZAY2BTxA4nWO8uAe77lSJXbeXv726q9nbc0/eNa24FPG05azHv5+189n4DTxPvZBg2kaPct/r2ePLoXHfnQ1xYDXy31/fbseQTEsmbeuk7f7E7YkP/SRkk60/YxTdlmD79OC6EU3Zi9XIdyof0prNKrpLBI+pBXcG0ljoPnmNzmPS9qnA0JEJQWviCmo2RniMDwEkX9jVyYfGA4Czi0LXXBaiybcYVUTlirN0Xh9+kZ4IundA68gIYeY4cjYR9TIIoDPePsp0p0CuGIK4XbbryysF1M71OG3kyd8Ws9F9zDax7HKH/dQI6Yp/zXGbAkEGtY3cBFb0PH0LLyeTHGUujrRPVP2f3LTuoAoEBf6+zz8n38lVzstePS6XyhY41DUyOk50an/pN1chANR2duLZvpE0 X-Forefront-Antispam-Report: CIP:192.86.86.210;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:hqxsv-psmtppxy02.rambus.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(7416014)(23010399003)(3023799007)(921020)(22082099003)(18002099003)(56012099006)(11063799006);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QfQeYaRoyvvAO3oH4jmsi04UHxJPVDVVBMVO0EmFGpC499n81XgnO8dBVdXT6zZ0FXHa4iDRvs/1O40r2PTtEQL8YfTKu600Bqof6ByurYNfYk64x8kEmQUmPqdA+TZihfAMnyh1hrTFyBGO+osiN2etN7ZzDGU8Qs1IX4oquqnSiHWAGTMgVLKzSMbQyYwsru6E90TWedKXhfwShXGIWNQQ5dSZdRzWJP9GIIcMcwHq62LIgawt1BeC03IJYUQCizvfosY08xciSPdPoh6VhQRUJW1O7vly5GI9KHqGY8L5XkDpKF49mrdev15dFoos7x9xo/Jif6C9zHnQLLnwu7GepGpkjtj/Ob4QvsSHusfzHQxxRT0nj5ej64RyTKTtimuH7bwnUApfmjo67zWK7Rc9zP079L7CQDLFw4UeC0axt0I+W5V8XaJpPOydQKq3 X-OriginatorOrg: rambus.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2026 20:31:20.7770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a557af88-fc53-4c7d-a0d7-08deddf90985 X-MS-Exchange-CrossTenant-Id: bd0ba799-c2b9-413c-9c56-5d1731c4827c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=bd0ba799-c2b9-413c-9c56-5d1731c4827c;Ip=[192.86.86.210];Helo=[hqxsv-psmtppxy02.rambus.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR04MB6616 From: Alex Ousherovitch Add device tree binding schema for the CRI CryptoManager Hub (CMH) hardware crypto accelerator. The binding covers the parent SoC-level node with register region, interrupt, DMA properties, and per-core child nodes identified by compatible string and unit address. Register the 'cri' vendor prefix for Cryptography Research, Inc. Co-developed-by: Saravanakrishnan Krishnamoorthy Signed-off-by: Saravanakrishnan Krishnamoorthy Signed-off-by: Alex Ousherovitch Reviewed-by: Joel Wittenauer Reviewed-by: Thi Nguyen --- .../devicetree/bindings/crypto/cri,cmh.yaml | 222 ++++++++++++++++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + 2 files changed, 224 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/cri,cmh.yaml diff --git a/Documentation/devicetree/bindings/crypto/cri,cmh.yaml b/Documentation/devicetree/bindings/crypto/cri,cmh.yaml new file mode 100644 index 000000000000..db41132e0591 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/cri,cmh.yaml @@ -0,0 +1,222 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/cri,cmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CRI CryptoManager Hub (CMH) Hardware Crypto Accelerator + +maintainers: + - Alex Ousherovitch + - Saravanakrishnan Krishnamoorthy + - Joel Wittenauer + +description: | + The CRI CryptoManager Hub (CMH) is a hardware cryptographic accelerator accessed + via a mailbox-based VCQ (Virtual Command Queue) interface. The host + writes VCQ command sequences into per-mailbox DMA queue buffers and + rings a doorbell; the CMH eSW processes them and signals completion + via interrupt. + + Supported algorithm families: SHA-2, SHA-3, SM3, AES, SM4, + ChaCha20-Poly1305, RSA, ECDSA, EdDSA, ECDH, SM2, ML-KEM, ML-DSA, + SLH-DSA, LMS, XMSS, DRBG. + +properties: + compatible: + const: cri,cmh + + reg: + maxItems: 1 + description: + SIC (System Interface Controller) MMIO region. Mailbox instance + registers are at offsets N * 0x1000 within this region. + + interrupts: + minItems: 1 + maxItems: 64 + description: + Per-mailbox completion/error interrupts from the CryptoManager Hub, + matching the real CMH ch_sys_interrupt_mbx[N-1:0] topology. + Entry i corresponds to MBX instance i. The driver maps each + configured mailbox (cri,mbx-instances) to its DT interrupt + index and registers a separate threaded IRQ handler per MBX. + + interrupt-names: + minItems: 1 + maxItems: 64 + items: + pattern: '^mbx[0-9]+$' + description: + Names for each mailbox interrupt, matching the interrupts array. + Format is "mbxN" where N is the mailbox instance index. + + cri,mbx-instances: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 64 + description: + Array of 0-based mailbox instance indices to configure. + Each index N maps to register offset N * 0x1000 within the + SIC region. If absent, defaults to instances 0 and 1. + + cri,mbx-slots-log2: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 64 + description: + Per-mailbox slot count as log2. Valid range 1..15. + Array length must match cri,mbx-instances. + Default is 5 (32 slots). + + cri,mbx-strides-log2: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 64 + description: + Per-mailbox stride (bytes per slot) as log2. Valid range 7..10. + Array length must match cri,mbx-instances. + Default is 7 (128 bytes per slot). + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^(hc|aes|sm4|sm3|hcq|qse|pke|drbg|ccp)@[0-9a-f]+$": + type: object + description: + Per-core-type child nodes. Each child represents one crypto core + instance available in the hardware. The driver enumerates these at + probe to discover which algorithm families are present. + + properties: + reg: + maxItems: 1 + description: + Hardware core ID for this core type (e.g. 0x02 for HC, 0x03 for AES). + Must match the CORE_ID_* values defined by the CMH hardware. + + cri,mbx: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pin this core instance to a specific mailbox instance index. + Multiple child nodes of the same core type may each specify a + different cri,mbx value to spread instances across mailboxes. + When absent, the driver auto-assigns a mailbox via round-robin + across the instances listed in cri,mbx-instances. + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + crypto@a4800000 { + compatible = "cri,cmh"; + reg = <0x0 0xa4800000 0x0 0x41000>; + interrupts = <1 2>; + interrupt-names = "mbx0", "mbx1"; + cri,mbx-instances = <0 1>; + cri,mbx-slots-log2 = <5 5>; + cri,mbx-strides-log2 = <7 7>; + #address-cells = <1>; + #size-cells = <0>; + + hc@2 { + reg = <0x02>; + }; + + aes@3 { + reg = <0x03>; + }; + + sm4@4 { + reg = <0x04>; + }; + + sm3@5 { + reg = <0x05>; + }; + + hcq@8 { + reg = <0x08>; + }; + + qse@9 { + reg = <0x09>; + }; + + pke@a { + reg = <0x0a>; + cri,mbx = <1>; + }; + + drbg@f { + reg = <0x0f>; + }; + + ccp@18 { + reg = <0x18>; + }; + }; + }; + + - | + /* Multi-instance: two AES cores on separate MBXes (future eSW support) */ + soc { + #address-cells = <2>; + #size-cells = <2>; + + crypto@a4800000 { + compatible = "cri,cmh"; + reg = <0x0 0xa4800000 0x0 0x41000>; + interrupts = <1 2>; + interrupt-names = "mbx0", "mbx1"; + cri,mbx-instances = <0 1>; + cri,mbx-slots-log2 = <5 5>; + cri,mbx-strides-log2 = <7 7>; + #address-cells = <1>; + #size-cells = <0>; + + hc@2 { + reg = <0x02>; + }; + + aes@3 { + reg = <0x03>; + cri,mbx = <0>; + }; + + /* Second AES instance at core ID 0x06, pinned to MBX 1 */ + aes@6 { + reg = <0x06>; + cri,mbx = <1>; + }; + + pke@a { + reg = <0x0a>; + cri,mbx = <1>; + }; + + drbg@f { + reg = <0x0f>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 396044f368e7..8b7187ea0194 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -375,6 +375,8 @@ patternProperties: description: Crane Connectivity Solutions "^creative,.*": description: Creative Technology Ltd + "^cri,.*": + description: Cryptography Research, Inc. "^crystalfontz,.*": description: Crystalfontz America, Inc. "^csky,.*": -- 2.43.7