From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E989C328B56; Sat, 11 Jul 2026 21:01:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783803727; cv=none; b=j2cnjBHmxfn/yZGCz32DLXhgBbVchsTfpBAvJI8DDiz+AfRrG3Frtv3/Lec75X08iBXkNpBF2oMx+hyxxk6ShxELDbw4WcLjk0oT7IM2T1p6AiA22jgSslROrcPJdWj2/trjhzyTccNCFNfo8eQ5MCKGSph3kslQz3Q2r6/ZOmw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783803727; c=relaxed/simple; bh=g+mNv/EntfDcFHQpYr7sm0Khvaj0iEaLqSyCIEuXEsI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OCHltmvDuDscji3aITuUIaZ5ZDgatu/+Y/SYNAXKm8Toymj3Fv03y1Xm1AV0XtIoCT9t0WiIQ5YR7R19IrKNwdcT9/SddcbsCBSsX9lXvrzLqiqgj3yw4fKBATIuxJIjuuvgfb5Tl6uT3m5MR1tYvIaOlozK1kpiTUPOSLqh1e4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=DZVBoKIU; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="DZVBoKIU" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6C51B11984E; Sat, 11 Jul 2026 23:01:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1783803714; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=VbelV6kMKLwt1ovagDKTC4aicrv3CH9g6/cgnCIdd/8=; b=DZVBoKIUBLjRDr5OVo9oweeK2Gi6GOhuBjVgosmYvZIBdK5L5NCHKsHJu/wdQeccN7rpsp nxKW4QY2IWqGkBP20/EfcSnsFzdbxrd464ZvDBHDJvaBUf5cDNKsrZx6ot5611muQ6PPBV 9rx3iS/boqxeAgI1sTebOuVmYbpCf1uGGL3SVWMPoyyYS9sNiBRHYaow3VzyWwq+m7J22O DGQ1noCsNrA5LZfsWSgTqyxeDKjsTir//I7VTGQQ6CJzk1mj48VZdhrNIZvmVpFsclnzUG /0lwyfKgyoq0ibwdnQjPAwZWJkGNhKH2U1bzyDHV20WO7kdxDRHRIxdG2O3wgw== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Bartosz Golaszewski , Conor Dooley , Krzysztof Kozlowski , Linus Walleij , Rob Herring , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 08/10] arm64: dts: st: Add pinmux nodes for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board Date: Sat, 11 Jul 2026 22:59:37 +0200 Message-ID: <20260711210131.236025-9-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260711210131.236025-1-marex@nabladev.com> References: <20260711210131.236025-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 Add new pinmux nodes for DH electronics STM32MP2 DHCOS SoM and BB board. The following pinmux nodes are added: - ETH2 pins - I2C8 pins - MCO1 pins - SDMMC1,2,3 pins - SPI1,8 pins - UART8,9 pins - USART1,2,6 pins Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Bartosz Golaszewski Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Linus Walleij Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 564 ++++++++++++++++++ 1 file changed, 564 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 456ece7f8ebc3..1aadbc6b47da9 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -182,6 +182,30 @@ pins5 { }; }; + /omit-if-no-ref/ + eth2_mdio_pins_a: eth2-mdio-0 { + pins1 { + pinmux = ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + eth2_mdio_sleep_pins_a: eth2-mdio-sleep-0 { + pins { + pinmux = , /* ETH_MDC */ + ; /* ETH_MDIO */ + }; + }; + /omit-if-no-ref/ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { pins { @@ -203,6 +227,68 @@ pins { }; }; + /omit-if-no-ref/ + eth2_rgmii_pins_b: eth2-rgmii-1 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + ; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* ETH_RGMII_CLK125 */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + eth2_rgmii_sleep_pins_b: eth2-rgmii-sleep-1 { + pins { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + + /omit-if-no-ref/ + mco1_pins_a: mco1-0 { + pins { + pinmux = ; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { @@ -394,6 +480,26 @@ pins2 { }; }; + /omit-if-no-ref/ + sdmmc1_b4_pins_b: sdmmc1-b4-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { @@ -419,6 +525,31 @@ pins3 { }; }; + /omit-if-no-ref/ + sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { @@ -431,6 +562,187 @@ pins { }; }; + /omit-if-no-ref/ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_pins_a: sdmmc3-b4-0 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <0>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_pins_b: sdmmc3-b4-1 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <0>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = ; /* SDMMC3_CMD */ + slew-rate = <2>; + drive-open-drain; + bias-disable; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + + /omit-if-no-ref/ + spi1_pins_a: spi1-0 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi1_sleep_pins_a: spi1-sleep-0 { + pins1 { + pinmux = , /* SPI1_SCK */ + , /* SPI1_MOSI */ + ; /* SPI1_MISO */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { @@ -471,6 +783,50 @@ pins { }; }; + /omit-if-no-ref/ + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_TX */ + , /* USART1_RTS */ + , /* USART1_CTS_NSS */ + ; /* USART1_RX */ + }; + }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { @@ -504,6 +860,50 @@ pins { }; }; + /omit-if-no-ref/ + usart2_pins_b: usart2-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart2_idle_pins_b: usart2-idle-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_CTS_NSS */ + ; /* USART2_RX */ + }; + }; + /omit-if-no-ref/ usart6_pins_a: usart6-0 { pins1 { @@ -547,6 +947,127 @@ pins { ; /* USART6_RX */ }; }; + + /omit-if-no-ref/ + usart6_pins_b: usart6-1 { + pins1 { + pinmux = ; /* USART6_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART6_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart6_idle_pins_b: usart6-idle-1 { + pins1 { + pinmux = ; /* USART6_TX */ + }; + pins2 { + pinmux = ; /* USART6_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart6_sleep_pins_b: usart6-sleep-1 { + pins { + pinmux = , /* USART6_TX */ + ; /* USART6_RX */ + }; + }; + + /omit-if-no-ref/ + uart8_pins_a: uart8-0 { + pins1 { + pinmux = , /* UART8_TX */ + ; /* UART8_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* UART8_RX */ + ; /* UART8_CTS_NSS */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = , /* UART8_TX */ + ; /* UART8_CTS_NSS */ + }; + pins2 { + pinmux = ; /* UART8_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = , /* UART8_TX */ + , /* UART8_RTS */ + , /* UART8_CTS_NSS */ + ; /* UART8_RX */ + }; + }; + + /omit-if-no-ref/ + uart9_pins_a: uart9-0 { + pins1 { + pinmux = , /* UART9_TX */ + ; /* UART9_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* UART9_RX */ + ; /* UART9_CTS_NSS */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart9_idle_pins_a: uart9-idle-0 { + pins1 { + pinmux = , /* UART9_TX */ + ; /* UART9_CTS_NSS */ + }; + pins2 { + pinmux = ; /* UART9_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* UART9_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart9_sleep_pins_a: uart9-sleep-0 { + pins { + pinmux = , /* UART9_TX */ + , /* UART9_RTS */ + , /* UART9_CTS_NSS */ + ; /* UART9_RX */ + }; + }; }; &pinctrl_z { @@ -569,6 +1090,25 @@ pins { }; }; + /omit-if-no-ref/ + i2c8_pins_b: i2c8-1 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c8_sleep_pins_b: i2c8-sleep-1 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ spi8_pins_a: spi8-0 { pins1 { @@ -592,4 +1132,28 @@ pins1 { ; /* SPI8_MISO */ }; }; + + /omit-if-no-ref/ + spi8_pins_b: spi8-1 { + pins1 { + pinmux = , /* SPI8_SCK */ + ; /* SPI8_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI8_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi8_sleep_pins_b: spi8-sleep-1 { + pins1 { + pinmux = , /* SPI8_SCK */ + , /* SPI8_MOSI */ + ; /* SPI8_MISO */ + }; + }; }; -- 2.53.0