Re: [PATCH v4 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Driver probe failure due to unsupported interrupt trigger type
- [Medium] Pinmux configuration error for RGMII2 transmit pins
--

--- Patch [3]: [PATCH v4 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board ---
commit eae5a6eae63323e628c7dec958171ae3d0b8c5fd
Author: Stefano Radaelli <stefano.r@variscite.com>

arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board

Add device tree support for the Variscite Symphony carrier board with
the VAR-SOM-AM62 system on module.

Link: https://www.variscite.it/product/single-board-computers/symphony-board/

> diff --git a/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts
> new file mode 100644
> index 0000000000000..24e67a131a7ec
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts

[ ... ]

> +&main_i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c0>;
> +	clock-frequency = <400000>;
> +	status = "okay";
> +
> +	/* GPIO expander */
> +	pca9534: gpio@20 {
> +		compatible = "nxp,pca9534";
> +		reg = <0x20>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pca9534>;
> +		#gpio-cells = <2>;
> +		gpio-controller;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&main_gpio1>;
> +		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;

[Severity: High]
Will this interrupt trigger type cause the pca9534 probe to fail?

The parent interrupt controller main_gpio1 uses the gpio-davinci driver, which
only supports edge triggers in its gpio_irq_type() callback. Requesting a
level-low trigger here will return -EINVAL during IRQ setup.

If the probe fails, could it also break the secondary Ethernet PHY
(cpsw3g_phy1) since it relies on this expander for its reset GPIO?

[ ... ]

> +	pinctrl_rgmii2: main-rgmii2-default-pins {
> +		bootph-all;
> +		pinctrl-single,pins = <
> +			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
> +			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
> +			AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
> +			AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
> +			AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
> +			AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
> +			AM62X_IOPAD(0x16c, PIN_INPUT, 0) /* (Y18) RGMII2_TD0 */
> +			AM62X_IOPAD(0x170, PIN_INPUT, 0) /* (AA18) RGMII2_TD1 */
> +			AM62X_IOPAD(0x174, PIN_INPUT, 0) /* (AD21) RGMII2_TD2 */
> +			AM62X_IOPAD(0x178, PIN_INPUT, 0) /* (AC20) RGMII2_TD3 */
> +			AM62X_IOPAD(0x168, PIN_INPUT_PULLDOWN, 0) /* (AE21) RGMII2_TXC */
> +			AM62X_IOPAD(0x164, PIN_INPUT, 0) /* (AA19) RGMII2_TX_CTL */

[Severity: Medium]
Should the RGMII2 transmit pins (TD0-TD3, TXC, TX_CTL) be configured as
outputs rather than inputs?

Using PIN_INPUT_PULLDOWN on RGMII2_TXC enables an active pull-down resistor
on the 125MHz transmit clock. Does this force the MAC output driver to
constantly fight the pull-down and degrade the high-speed signal integrity?

> +		>;
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1783864932.git.stefano.r@variscite.com?part=3