Re: [PATCH v2 3/5] dt-bindings: clock: qcom: Add Maili global clock controller

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing Block Control Reset (BCR) definition for the newly added QUPV3_WRAP5 hardware block.
--

--- Patch [3]: [PATCH v2 3/5] dt-bindings: clock: qcom: Add Maili global clock controller ---
commit 71e15b2f70937d7e5560b3d037438455bb0ef7dc
Author: Taniya Das <taniya.das@oss.qualcomm.com>

dt-bindings: clock: qcom: Add Maili global clock controller

Add device tree bindings for the global clock controller (GCC) on
the Qualcomm Maili SoC by extending the existing Qualcomm Hawi GCC
bindings, since the Maili GCC is identical to the Hawi GCC apart
from a few additional clocks.

[ ... ]

> diff --git a/include/dt-bindings/clock/qcom,maili-gcc.h b/include/dt-bindings/clock/qcom,maili-gcc.h
> new file mode 100644
> index 0000000000000..9bea90adb988e
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,maili-gcc.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_MAILI_H
> +#define _DT_BINDINGS_CLK_QCOM_GCC_MAILI_H
> +
> +#include "qcom,hawi-gcc.h"
> +
> +/* Maili has below additional clocks on top of Hawi */
> +#define GCC_QUPV3_WRAP5_CORE_2X_CLK				188
> +#define GCC_QUPV3_WRAP5_CORE_CLK				189
> +#define GCC_QUPV3_WRAP5_QSPI_REF_CLK				190
> +#define GCC_QUPV3_WRAP5_QSPI_REF_CLK_SRC			191
> +#define GCC_QUPV3_WRAP5_S0_CLK					192
> +#define GCC_QUPV3_WRAP5_S0_CLK_SRC				193
> +#define GCC_QUPV3_WRAP_5_M_AHB_CLK				194
> +#define GCC_QUPV3_WRAP_5_S_AHB_CLK				195

[Severity: Medium]
Is this block missing the corresponding Block Control Reset (BCR) definition
for the newly added QUPV3_WRAP5 hardware block?

Since the WRAP5 clocks are exposed here, it seems a reset definition such as
GCC_QUPV3_WRAPPER_5_BCR is needed as well. Without it, the clock controller
driver won't be able to expose the reset for the QUPv3 WRAP5 block, which 
could prevent peripherals attached to it from initializing properly.

> +
> +#endif

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260713-maili_initial_clock-v2-0-79548f0bb58f@oss.qualcomm.com?part=3