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([188.243.183.76]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493eb6f3dcdsm354106345e9.3.2026.07.13.06.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 06:12:33 -0700 (PDT) From: Artem Shimko To: netdev@vger.kernel.org, Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Artem Shimko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH net-next 1/2] dt-bindings: net: add DAPU Telecom DAP8211R(I) PHY binding Date: Mon, 13 Jul 2026 16:12:22 +0300 Message-ID: <20260713131223.279555-2-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260713131223.279555-1-a.shimko.dev@gmail.com> References: <20260713131223.279555-1-a.shimko.dev@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add device tree binding documentation for the DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY. The PHY supports TX and RX clock delays in 150 ps steps from 0 to 2250 ps, with a default of 1950 ps if not specified. The tx-inverted-clk flag provides a vendor-specific extension for boards where PCB trace length or MAC requirements necessitate 180-degree clock phase shift. Signed-off-by: Artem Shimko --- .../bindings/net/dapu,dap8211r.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dapu,dap8211r.yaml diff --git a/Documentation/devicetree/bindings/net/dapu,dap8211r.yaml b/Documentation/devicetree/bindings/net/dapu,dap8211r.yaml new file mode 100644 index 000000000000..208a82f779d6 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dapu,dap8211r.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dapu,dap8211r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY + +maintainers: + - Artem Shimko + +description: | + The DAP8211R(I) is a Gigabit Ethernet PHY with RGMII interface, + supporting IEEE 802.3az Energy Efficient Ethernet, IEEE 1588 SyncE, + and an internal packet generator for diagnostics. + + Specifications: + - 10BASE-Te, 100BASE-TX, 1000BASE-T + - RGMII with configurable TX/RX clock delays (150 ps steps, 0-2250 ps) + - IEEE 802.3az-2010 Energy Efficient Ethernet + - IEEE 1588 SyncE support + - Internal packet generator and checker for link diagnostics + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + const: ethernet-phy-id0008.011b + + reg: + maxItems: 1 + + rx-internal-delay-ps: + description: + RGMII RX clock delay in picoseconds. The PHY supports 150 ps steps + from 0 to 2250 ps. If not specified, defaults to 1950 ps. If the + requested value does not exactly match a supported step, the driver + selects the nearest supported value and issues a warning. + enum: [0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, + 1650, 1800, 1950, 2100, 2250] + default: 1950 + + tx-internal-delay-ps: + description: + RGMII TX clock delay in picoseconds. The PHY supports 150 ps steps + from 0 to 2250 ps. If not specified, defaults to 1950 ps. If the + requested value does not exactly match a supported step, the driver + selects the nearest supported value and issues a warning. + enum: [0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, + 1650, 1800, 1950, 2100, 2250] + default: 1950 + + tx-inverted-clk: + $ref: /schemas/types.yaml#/definitions/flag + description: + If present, the RGMII TX clock to the MAC is inverted (180 degree + phase shift relative to the data lines). This is a vendor-specific + extension for boards where PCB trace length or MAC requirements + necessitate clock inversion. Only use this property after hardware + signal integrity validation. + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + rx-internal-delay-ps = <1050>; + tx-internal-delay-ps = <1150>; + tx-inverted-clk; + }; + }; \ No newline at end of file -- 2.43.0