From: sashiko-bot@kernel.org
To: "Jia Wang" <wangjia@ultrarisc.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 1/3] dt-bindings: pci: ultrarisc: add required DP1000 PCIe clocks
Date: Tue, 14 Jul 2026 01:24:53 +0000 [thread overview]
Message-ID: <20260714012454.55D1B1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260714-ultrarisc-pci-clk-v3-1-e72723fc0ef1@ultrarisc.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Missing driver clock management. The DP1000 PCIe driver fails to implement support for the newly mandated `core`, `dbi`, and `aux` clocks, leading to unclocked hardware register accesses.
--
--- Patch [1]: [PATCH v3 1/3] dt-bindings: pci: ultrarisc: add required DP1000 PCIe clocks ---
commit 04ce10fff5fc6c7c7dc6e7380ab1ae6a1209bb14
Author: Jia Wang <wangjia@ultrarisc.com>
dt-bindings: pci: ultrarisc: add required DP1000 PCIe clocks
This commit mandates that DP1000 PCIe controller nodes provide the standard
DesignWare clock names "core", "dbi", and "aux" in the device tree bindings.
> diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> --- a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> @@ -43,6 +43,18 @@ properties:
[ ... ]
> + clocks:
> + items:
> + - description: PCIe core clock
> + - description: Data Bus Interface (DBI) clock
> + - description: Auxiliary clock
> +
> + clock-names:
> + items:
> + - const: core
> + - const: dbi
> + - const: aux
[Severity: High]
This is a pre-existing issue, but since these clocks are now formally required
by the binding, does the pcie-ultrarisc driver also need to be updated to
manage them?
Looking at drivers/pci/controller/dwc/pcie-ultrarisc.c, ultrarisc_pcie_probe()
does not appear to fetch or enable these clocks. Because of this, hardware
registers are accessed before clocks are explicitly enabled by the driver:
drivers/pci/controller/dwc/pcie-ultrarisc.c:ultrarisc_pcie_host_init() {
...
val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
...
}
Will this unclocked hardware register access trigger a synchronous bus error
and kernel panic during the device probe path on boot?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260714-ultrarisc-pci-clk-v3-0-e72723fc0ef1@ultrarisc.com?part=1
next prev parent reply other threads:[~2026-07-14 1:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-14 1:11 [PATCH v3 0/3] PCI: ultrarisc: Add DP1000 PCIe clock support Jia Wang via B4 Relay
2026-07-14 1:11 ` [PATCH v3 1/3] dt-bindings: pci: ultrarisc: add required DP1000 PCIe clocks Jia Wang via B4 Relay
2026-07-14 1:24 ` sashiko-bot [this message]
2026-07-14 1:11 ` [PATCH v3 2/3] PCI: ultrarisc: get and enable " Jia Wang via B4 Relay
2026-07-14 1:18 ` sashiko-bot
2026-07-14 1:11 ` [PATCH v3 3/3] PCI: ultrarisc: allow DP1000 driver to build as module Jia Wang via B4 Relay
2026-07-14 1:15 ` sashiko-bot
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