Devicetree
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From: sashiko-bot@kernel.org
To: "Liu Changjie" <liucj1228@outlook.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add LCKFB Taishan Pi 3M
Date: Tue, 14 Jul 2026 07:11:08 +0000	[thread overview]
Message-ID: <20260714071109.5BA4E1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <MN0PR19MB6091D3101FD2D8F940F0CE4DACF92@MN0PR19MB6091.namprd19.prod.outlook.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The device tree uses an undocumented and unsupported vendor property `maxio,clk-out-frequency-hz` in the Ethernet PHY node, which will be ignored by the upstream kernel, causing the GMAC reference clock to remain unconfigured.
--

--- Patch [2]: [PATCH v2 2/2] arm64: dts: rockchip: Add LCKFB Taishan Pi 3M ---
commit 7ee3e6144c52507192ef8cc196563da5f89d4b8e
Author: Liu Changjie <liucj1228@outlook.com>

arm64: dts: rockchip: Add LCKFB Taishan Pi 3M

This adds the device tree for the LCKFB Taishan Pi 3M board based on the
Rockchip RK3576 SoC. It describes various hardware components including the
RK806 supplies, eMMC, SD card, Gigabit Ethernet, and others. The patch also
attempts to configure the MAE0621A PHY CLKOUT to supply the GMAC reference
clock at 125 MHz.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3576-lckfb-tspi-3m.dts b/arch/arm64/boot/dts/rockchip/rk3576-lckfb-tspi-3m.dts
> new file mode 100644
> index 0000000000000..bfddce2a94fb8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3576-lckfb-tspi-3m.dts

[ ... ]

> +&mdio0 {
> +	rgmii_phy0: ethernet-phy@1 {
> +		compatible = "ethernet-phy-id7b74.4412";
> +		reg = <0x1>;
> +		maxio,clk-out-frequency-hz = <125000000>;
[Severity: High]
Is this maxio,clk-out-frequency-hz property supported by an upstream PHY
driver?

It appears maxio is an unregistered vendor prefix, and this property is not
defined in upstream device tree bindings, which will cause make dtbs_check
to fail.

Since there is no upstream driver matching the 7b74.4412 ID, the PHY will
likely bind to the generic genphy driver which ignores this property.
Because the device tree specifies a hardware reset below via reset-gpios, the
PHY will be reset during initialization, clearing any clock configuration
provided by the bootloader.

Will this result in the GMAC reference clock remaining unconfigured and
breaking Ethernet functionality on this board?

> +		pinctrl-names = "default";
> +		pinctrl-0 = <&gmac0_phy_reset>;
> +		reset-assert-us = <20000>;
> +		reset-deassert-us = <100000>;
> +		reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/MN0PR19MB60918292CC2D566716815F26ACF92@MN0PR19MB6091.namprd19.prod.outlook.com?part=2

  reply	other threads:[~2026-07-14  7:11 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-07  3:07 [PATCH 1/2] dt-bindings: arm: rockchip: Add LCKFB Taishan Pi 3M Liu Changjie
2026-05-13 19:21 ` Rob Herring (Arm)
2026-07-14  6:53 ` [PATCH v2 0/2] arm64: dts: " Liu Changjie
2026-07-14  6:54   ` [PATCH v2 2/2] " Liu Changjie
2026-07-14  7:11     ` sashiko-bot [this message]
2026-07-14  6:54   ` [PATCH v2 1/2] dt-bindings: arm: " Liu Changjie

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