Re: [PATCH v4 6/6] arm64: dts: qcom: shikra: Add ICE, TRNG and QCE nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `sdhc_ice` node uses the conceptually incorrect power domain identifier `RPMHPD_CX` (an RPMh macro) instead of the correct `RPMPD_VDDCX` (an RPM SMD macro).
--

--- Patch [6]: [PATCH v4 6/6] arm64: dts: qcom: shikra: Add ICE, TRNG and QCE nodes ---
commit ac9385e506169b93982d324a8fd1c94a56ace5b0
Author: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>

arm64: dts: qcom: shikra: Add ICE, TRNG and QCE nodes

This commit adds device tree nodes describing the crypto hardware blocks
present on the Qualcomm Shikra platform, including the BAM DMA controller,
QCE engine, TRNG, and Inline Crypto Engine (ICE). It also connects the
SDHC controller to ICE to support inline encryption.

> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 4e5bc9e17c8ed..a95e2140416c2 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
[ ... ]
> @@ -604,6 +645,17 @@ opp-384000000 {
>  			};
>  		};
>  
> +		sdhc_ice: crypto@4748000 {
> +			compatible = "qcom,shikra-inline-crypto-engine",
> +				     "qcom,inline-crypto-engine";
> +			reg = <0x0 0x04748000 0x0 0x18000>;
> +			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>,
> +				 <&gcc GCC_SDCC1_AHB_CLK>;
> +			clock-names = "core",
> +				      "iface";
> +			power-domains = <&rpmpd RPMHPD_CX>;

[Severity: Low]
Does this code use an RPMh power domain macro (RPMHPD_CX) for an RPM SMD
power controller instead of RPMPD_VDDCX?

The sdhc_ice node references the rpmpd (RPM SMD) provider but incorrectly
assigns it the RPMHPD_CX macro. Because dt-bindings/power/qcom-rpmpd.h
explicitly includes dt-bindings/power/qcom,rpmhpd.h, the macro is defined
and evaluates to 0, which happens to match RPMPD_VDDCX. 

While this avoids build errors and runtime impact, should this use the
correct RPMPD_VDDCX macro to prevent a semantic mismatch?

> +		};
> +
>  		qupv3_0: geniqup@4ac0000 {
>  			compatible = "qcom,geni-se-qup";
>  			reg = <0x0 0x04ac0000 0x0 0x2000>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714-b4-shikra_crypto_changse-v4-0-06a4ea97c209@oss.qualcomm.com?part=6