Re: [PATCH net-next v10 2/9] dt-bindings: net: lan9645x: add LAN9645X switch bindings

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] DT binding schema strictly prohibits `mdio` bus nodes, breaking the ability to define integrated PHYs.
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--- Patch [2]: [PATCH net-next v10 2/9] dt-bindings: net: lan9645x: add LAN9645X switch bindings ---
commit d0ca8cd625881ac3b8529fd977bdb0c8a0c3b129
Author: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>

dt-bindings: net: lan9645x: add LAN9645X switch bindings

Add bindings for LAN9645X switch. We use a fallback compatible for the
smallest SKU microchip,lan96455s-switch.

> diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml
> new file mode 100644
> index 0000000000000..043fb48922b41
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml

[ ... ]

> +required:
> +  - compatible
> +  - reg
> +  - ethernet-ports
> +
> +unevaluatedProperties: false

[Severity: Medium]
Will this schema reject valid hardware descriptions that include an mdio child
node for the integrated PHYs?

Since the schema sets unevaluatedProperties: false without defining or
referencing an mdio property, any mdio node defined in a device tree will
be rejected as an illegal property.

> +
> +examples:
> +  - |
> +    ethernet-switch@4000 {
> +        compatible = "microchip,lan96459f-switch", "microchip,lan96455s-switch";
> +        reg = <0x4000 0x244>;
> +
> +        ethernet-ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            ethernet-port@0 {
> +                reg = <0>;
> +                phy-mode = "gmii";
> +                phy-handle = <&cuphy0>;

[Severity: Medium]
Does the schema allow defining the integrated PHY nodes referenced here?

The example demonstrates the necessity of phy-handle pointers to integrated
PHY nodes (such as &cuphy0), yet the schema's constraints make it
structurally impossible to validly define the MDIO bus for those PHYs.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260713-dsa_lan9645x_switch_driver_base-v10-0-a4886a08fb15@microchip.com?part=2