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Tue, 14 Jul 2026 12:14:11 -0700 (PDT) From: Coia Prant To: kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, andrew+netdev@lunn.ch, robh@kernel.org, krzk+dt@kernel.org, heiko@sntech.de Cc: netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Coia Prant Subject: [RFC PATCH 04/10] dt-bindings: net: pcs: add rockchip,rk3568-xpcs binding Date: Wed, 15 Jul 2026 03:08:32 +0800 Message-ID: <20260714191341.690906-5-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260714191341.690906-1-coiaprant@gmail.com> References: <20260714191341.690906-1-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add device tree binding documentation for the Synopsys DesignWare XPCS integrated on the Rockchip RK3568 SoC. The XPCS is accessed over the APB3 bus and internally connected to a Naneng Combo SerDes PHY. It supports 1000BASE-X, SGMII, and QSGMII modes, with four MII ports. The binding describes: - Required properties: compatible, reg, clocks, clock-names - Optional properties: phys, phy-names, power-domains - pcs-mii sub-nodes for each MII port (reg 0..3) Signed-off-by: Coia Prant --- .../bindings/net/pcs/rockchip-dwxpcs.yaml | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/rockchip-dwxpcs.yaml diff --git a/Documentation/devicetree/bindings/net/pcs/rockchip-dwxpcs.yaml b/Documentation/devicetree/bindings/net/pcs/rockchip-dwxpcs.yaml new file mode 100644 index 0000000000000..14fadf67c793a --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/rockchip-dwxpcs.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/rockchip-dwxpcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 Synopsys DesignWare Ethernet PCS + +maintainers: + - Coia Prant + +description: | + Rockchip RK3568 SoC integrates a Synopsys DesignWare Ethernet Physical + Coding Sublayer (XPCS). + The PCS provides an interface between the Media Access Control (MAC) + and the Physical Medium Attachment (PMA) sublayer through a Media + Independent Interface (GMII). + + The XPCS is accessed over the APB3 bus and internally connected to a + Naneng Combo SerDes PHY. + It supports 1000BASE-X, SGMII and QSGMII modes. + + The block contains four MII ports (pcs-mii@0..3) that can be + individually enabled and routed to one of the Ethernet GMAC controllers + via the pcs-handle property in the MAC device tree node. + +properties: + compatible: + const: rockchip,rk3568-xpcs + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + description: | + Base address and size of the XPCS register space mapped over the + APB3 bus. + maxItems: 1 + + clocks: + description: | + Clock sources for the XPCS: + - csr: APB3 bus interface clock (clk_csr_i), required for register + access. + - eee: EEE clock (clk_eee_i), required for Energy Efficient + Ethernet (EEE) operation. + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: csr + - const: eee + + phys: + description: | + The phandle of SerDes PHY (Naneng Combo PHY) that provides + the serial lanes for 1000BASE-X / SGMII / QSGMII. + The SerDes must be powered on and initialised before any XPCS + register access. + maxItems: 1 + + phy-names: + const: serdes + + power-domains: + description: | + Power domain for the XPCS. + On RK3568 this is typically the PD_PIPE power domain, which also + supplies the SerDes PHY. + maxItems: 1 + +patternProperties: + "^pcs-mii@[0-3]$": + type: object + description: | + One of the four MII ports of the XPCS. + The port number is specified by the reg property (0..3). + The port is linked to an Ethernet MAC controller via the + pcs-handle property in the MAC's device tree node. + + properties: + reg: + minimum: 0 + maximum: 3 + description: | + MII port number of PCS. + + status: true + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + pcs@fda00000 { + compatible = "rockchip,rk3568-xpcs"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xfda00000 0x0 0x200000>; + clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names = "csr", "eee"; + phys = <&combphy2 PHY_TYPE_SGMII>; + phy-names = "serdes"; + power-domains = <&power RK3568_PD_PIPE>; + + pcs-mii@0 { + reg = <0>; + }; + }; -- 2.47.3