Re: [PATCH v3 2/4] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Double RGMII delay insertion on gmac2 due to incorrect phy-mode.
- [High] Conceptual misuse of 'rgmii-id' for MAC-side delays on gmac1 and missing driver implementation causing double-delays.
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--- Patch [2]: [PATCH v3 2/4] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board ---
commit 1726dd01c79b5342df101114181fa6297c1dabde
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board

This commit adds the device tree for the Intel SoCFPGA Agilex5 SoCDK TSN
Config2 board variant. This configuration enables gmac1 as a TSN port
alongside the standard gmac2 Ethernet port.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts

[ ... ]

> +&gmac1 {
> +	status = "okay";
> +	compatible = "altr,socfpga-stmmac-agilex5-tsn",
> +		     "altr,socfpga-stmmac-agilex5",
> +		     "snps,dwxgmac-2.10";
> +	phy-mode = "rgmii-id";

[Severity: High]
The commit message states that phy-mode is set to "rgmii-id" to reflect
MAC-side delays, relying on the "altr,socfpga-stmmac-agilex5-tsn" compatible
string for the driver to detect the converter and strip the delay bits.

Since the driver implementation for this board-specific compatible string does
not appear to be included in this patch series, won't the driver fall back to
"altr,socfpga-stmmac-agilex5" and fail to strip the delay bits?

Additionally, if the MAC side (FPGA soft IP) already provides the delays,
should the phy-mode simply be set to "rgmii" to intrinsically prevent the PHY
from adding its own delays, instead of relying on a driver workaround?

> +	phy-handle = <&emac1_phy0>;
> +	max-frame-size = <9000>;

[ ... ]

> +&gmac2 {
> +	status = "okay";
> +	phy-mode = "rgmii-id";

[Severity: High]
The commit message notes this board retains the standard gmac2 Ethernet port.
In the baseline Agilex5 SoCDK, the HPS MAC intrinsically provides TX/RX clock
delays for gmac2, so phy-mode is typically set to "rgmii".

Does setting phy-mode to "rgmii-id" here cause the PHY to inject a second,
erroneous set of delays on top of the native MAC hardware delays, potentially
breaking RGMII link timing for the standard Ethernet port?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714021303.30042-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2