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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13cd42b2c0bsm471669c88.8.2026.07.15.04.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 04:16:29 -0700 (PDT) From: Wei Deng To: mani@kernel.org Cc: dmitry.baryshkov@oss.qualcomm.com, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, brgl@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, wenst@chromium.org, mengshi.wu@oss.qualcomm.com, quic_chezhou@quicinc.com, cheng.jiang@oss.qualcomm.com, shuai.zhang@oss.qualcomm.com, jinwang.li@oss.qualcomm.com, xiuzhuo.shang@oss.qualcomm.com Subject: Re: [PATCH 3/3] power: sequencing: pcie-m2: Deassert W_DISABLE2# when no UART serdev is created Date: Wed, 15 Jul 2026 16:46:22 +0530 Message-Id: <20260715111622.2561730-1-wei.deng@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=Ife3n2qa c=1 sm=1 tr=0 ts=6a576c0f cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=cm27Pg_UAAAA:8 a=RcxsvD7BqTzStQuQcmYA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: UBF_JAO-ENH-yZgYRTeX9f-8_yjT4KXo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDEwOSBTYWx0ZWRfX77rehXhtT5vx e0wCMH4rZUBMNFaB/KoqHNvGPco0rofqfo/+x/mt0lWgY0rqhgbZrD9GBIDcjineJR5jdme/qDS JCC6JgxXv9nbPws74DAkk06Qru/22j/LT4QSh/GgIBrMez39TyR94QW78O/0rEvdCHHb7shmSgq AK8ZxLg1MWR2jbNJndPEbquLZATh/J2R2F/7XA2tbeOmNp890nzGQauKEmmDC8ylAPrfiB8XfI3 NldX9q59i6dBoxodkfQpqL+S7tkzZZr3P1hALKFrN6Awk6oB3rV+4EsLFNHbmTeUKiLkYADsUG4 T2ATZhOoFd4+QXijVB6GNgS5rqslGh4jASYxj8d4VDpaaIMaIyRVdO2BuZHAgUg90E3jje+ZmZ7 6thYVMmK7D1+q+GjGAC/f2zAKmRK+KWFu67jozC0sfZfi13XRZNVd08Nwlqd9nhc/HDD6EBFwv9 H6K2fCaN9kJELTOAM2A== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDEwOSBTYWx0ZWRfX0VKorRO12P0m VT8kJ8pEUS0fyqyFast9V6PgWeygUqhWD3E3itq+2iCBFB5L0Ptwwpr4ptg3FKuTfc+fbWrBEni jRkw6lak5Ofzo/8RyBYFbqp9YMyTdas= X-Proofpoint-GUID: UBF_JAO-ENH-yZgYRTeX9f-8_yjT4KXo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_02,2026-07-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150109 On Tue, 14 Jul 2026, Manivannan Sadhasivam wrote: > On Mon, Jul 13, 2026 at 02:46:16PM +0530, Wei Deng wrote: > > On Thu, 9 Jul 2026, Dmitry Baryshkov wrote: > > > On Thu, Jul 09, 2026 at 12:59:42PM +0530, Wei Deng wrote: > > > > The pwrseq_m2_pci_ids[] table lists PCIe BT devices that use UART as the > > > > BT transport and need a UART serdev created by the driver. When a PCIe > > > > device under the M.2 connector does not match any entry in this table, > > > > no UART serdev is created. > > > > > > > > However, the BT subsystem of such a device may still require W_DISABLE2# > > > > to be deasserted to power up. Rather than adding every possible non-UART > > > > BT device ID to the table, add an else branch that deasserts W_DISABLE2# > > > > whenever a PCIe device is detected under the connector but does not match > > > > a UART BT entry. This allows any BT interface on the card (USB or other) > > > > to enumerate without requiring explicit knowledge of its device ID. > > > > > > > > The primary use case is USB BT variants of combo chips that share the > > > > same PCIe device ID as their UART counterpart (e.g. WCN7851 NCM865 USB, > > > > sub 0x3378, vs NCM865A UART, sub 0x337c): no UART serdev is needed, but > > > > W_DISABLE2# must be deasserted so the USB BT device can enumerate. > > > > > > Instead of forcibly toggling it, would it be more sensible to tie pwrseq > > > into the USB too? The onboard-usb-dev implements the same idea (of > > > powering up the USB device), but it predates pwrseq. > > > > > > -- > > > With best wishes > > > Dmitry > > > > > > > Hi Dmitry, > > > > There is a patch series from Chen-Yu Tsai that appears to implement what > > you suggested: > > > > [PATCH v4 00/14] arm64: mediatek: Add M.2 E-key slot on Chromebooks > > https://lore.kernel.org/all/20260709095726.704448-1-wenst@chromium.org/ > > > > We have been testing this on the Qualcomm Hamoa IoT EVK with both UART BT > > and USB BT M.2 cards. Is this the direction you had in mind? > > > > IMO, we should move towards Chen's series. > > - Mani Agreed. While testing Chen-Yu's v4 on the Qualcomm Hamoa IoT EVK with a board that needs to support both USB and UART BT cards, we found that the USB hub holds a reference to the "usb" pwrseq target permanently (acquired in hub_activate() and never released). When the UART BT driver later calls pwrseq_power_off(), the bt_unit enable_count only drops to 1 and bt_disable() is never invoked, leaving W_DISABLE2# deasserted. This prevents the BT chip from being properly reset, causing the next btmgmt power on to fail. This issue is addressed in v5 Patch 14 by splitting the Bluetooth pwrseq unit into independent uart and usb units, each with their own reference count: [PATCH v5 00/16] arm64: mediatek: Add M.2 E-key slot on Chromebooks https://lore.kernel.org/all/20260715085348.3457359-1-wenst@chromium.org/ The series still needs review from you and other maintainers. -- Best Regards, Wei Deng