Devicetree
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From: sashiko-bot@kernel.org
To: "Janani Sunil" <janani.sunil@analog.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v6 1/5] spi: dt-bindings: Add spi-device-addr peripheral property
Date: Wed, 15 Jul 2026 11:48:21 +0000	[thread overview]
Message-ID: <20260715114822.6019C1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260715-ad5529r-driver-v6-1-cfdf8b9f5ee3@analog.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `spi-device-addr` array property groups multiple physical chips under a single Device Tree node, which violates core DT architecture and precludes describing per-chip resources.
--

--- Patch [1]: [PATCH v6 1/5] spi: dt-bindings: Add spi-device-addr peripheral property ---
commit 039a81f5133684e72f9b6f61fd5df1550f9b8b54
Author: Janani Sunil <janani.sunil@analog.com>

spi: dt-bindings: Add spi-device-addr peripheral property

This commit adds a generic spi-device-addr property to describe multiple
hardware addresses for SPI devices that share a single chip select. The
property is defined as a uint32-array to be placed on the SPI peripheral
node.

> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml

[ ... ]

> @@ -142,6 +142,11 @@ properties:
>      minItems: 2
>      maxItems: 4
>  
> +  spi-device-addr:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description:
> +      Device address used when multiple peripherals share a single chip select.

[Severity: Medium]
Does grouping multiple physical chips under a single Device Tree node using an
array property conflict with core DT architecture?

If multiple addresses are listed here, it becomes impossible to describe
distinct per-chip hardware resources, such as individual interrupts, clocks,
or power supplies for those physical chips.

Would it be more appropriate to model the shared CS as a bridge or bus node
with #address-cells = <1>, and represent each physical chip as a distinct
child node with its own reg and discrete properties? 

Since Device Tree bindings form a permanent ABI, establishing this array
pattern might permanently constrain drivers needing to represent per-chip
resources on shared chip selects.

> +
>    st,spi-midi-ns:
>      deprecated: true
>      description: |

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260715-ad5529r-driver-v6-0-cfdf8b9f5ee3@analog.com?part=1

  reply	other threads:[~2026-07-15 11:48 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-15 11:41 [PATCH v6 0/5] iio: dac: Add support for AD5529R DAC Janani Sunil
2026-07-15 11:41 ` [PATCH v6 1/5] spi: dt-bindings: Add spi-device-addr peripheral property Janani Sunil
2026-07-15 11:48   ` sashiko-bot [this message]
2026-07-15 13:09   ` Mark Brown
2026-07-15 13:29     ` Nuno Sá
2026-07-15 13:37       ` Mark Brown
2026-07-15 11:41 ` [PATCH v6 2/5] dt-bindings: iio: adc: microchip,mcp3564: Add spi-device-addr Janani Sunil
2026-07-15 11:50   ` sashiko-bot
2026-07-15 11:41 ` [PATCH v6 3/5] dt-bindings: iio: adc: microchip,mcp3911: " Janani Sunil
2026-07-15 11:52   ` sashiko-bot
2026-07-15 11:41 ` [PATCH v6 4/5] dt-bindings: iio: dac: Add AD5529R Janani Sunil
2026-07-15 11:52   ` sashiko-bot
2026-07-15 11:41 ` [PATCH v6 5/5] iio: dac: Add AD5529R DAC driver support Janani Sunil
2026-07-15 11:52   ` sashiko-bot

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