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[90.182.112.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49508725c0bsm149543755e9.2.2026.07.15.04.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 04:40:55 -0700 (PDT) Date: Wed, 15 Jul 2026 13:40:53 +0200 From: Joshua Crofts To: Esben Haabendal Cc: "Jonathan Cameron" , "Lars-Peter Clausen" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Martin Kepplinger" , "Sean Nyekjaer" , "David Lechner" , Nuno =?ISO-8859-1?Q?S=E1?= , "Andy Shevchenko" , "Martin Kepplinger" , , , Subject: Re: [PATCH 2/2] iio: accel: mma8452: Allow open drain interrupt pin configuration Message-ID: <20260715134053.000012d4@gmail.com> In-Reply-To: <87pl0oo5iq.fsf@geanix.com> References: <20260715-mma8452-open-drain-v1-0-b1dd2a440c60@geanix.com> <20260715-mma8452-open-drain-v1-2-b1dd2a440c60@geanix.com> <20260715104542.0000433d@gmail.com> <87pl0oo5iq.fsf@geanix.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 15 Jul 2026 13:29:17 +0200 Esben Haabendal wrote: ... > >> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c > >> index 7d683686dd9d..a20c02ce0b9c 100644 > >> --- a/drivers/iio/accel/mma8452.c > >> +++ b/drivers/iio/accel/mma8452.c > >> @@ -81,6 +81,8 @@ > >> #define MMA8452_CTRL_REG2_RST BIT(6) > >> #define MMA8452_CTRL_REG2_MODS_SHIFT 3 > >> #define MMA8452_CTRL_REG2_MODS_MASK 0x1b > >> +#define MMA8452_CTRL_REG3 0x2c > >> +#define MMA8452_CTRL_REG3_PP_OD BIT(0) > > > > I know that the defines are completely incorrectly aligned, but please > > ensure that at least all the defines in this block are aligned. > > > > Also, consider sending a patch which aligns all the other defines. > > How are they incorrectly aligned? > The all look perfectly fine here (visual tabs space set to 8). > Should I convert all the tabs used for alignment to spaces? > > AFAICS, I have added the defines with same alignment as the other > defines in that block. I believe the misalignment is only a visual > artifact caused by the diff format. Ah, I meant it as currently the defines look like this: #define MMA8452_WHO_AM_I 0x0d #define MMA8452_DATA_CFG 0x0e #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) #define MMA8452_DATA_CFG_FS_2G 0 but instead should look like this: #define MMA8452_WHO_AM_I 0x0d #define MMA8452_DATA_CFG 0x0e #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) #define MMA8452_DATA_CFG_FS_2G 0 I'm not sure if this was intentional or not in the original implementation. ... > After reordering member fields, I get this: > > struct mma8452_data { > struct i2c_client * client; /* 0 8 */ > struct mutex lock __attribute__((__aligned__(8))); /* 8 24 */ > struct iio_mount_matrix orientation; /* 32 72 */ > /* --- cacheline 1 boundary (64 bytes) was 40 bytes ago --- */ > const struct mma_chip_info * chip_info; /* 104 8 */ > struct regulator * vdd_reg; /* 112 8 */ > struct regulator * vddio_reg; /* 120 8 */ > /* --- cacheline 2 boundary (128 bytes) --- */ > struct { > __be16 channels[3]; /* 128 6 */ > > /* XXX 2 bytes hole, try to pack */ > > __s64 ts __attribute__((__aligned__(8))); /* 136 8 */ > } __attribute__((__aligned__(8))) buffer __attribute__((__aligned__(8))); /* 128 16 */ > > /* XXX last struct has 1 hole */ > > int sleep_val; /* 144 4 */ > u8 ctrl_reg1; /* 148 1 */ > u8 data_cfg; /* 149 1 */ > bool open_drain; /* 150 1 */ > > /* size: 152, cachelines: 3, members: 11 */ > /* padding: 1 */ > /* member types with holes: 1, total: 1 */ > /* forced alignments: 2 */ > /* last cacheline: 24 bytes */ > } __attribute__((__aligned__(8))); This looks great! -- Kind regards CJD