Re: [RFC PATCH 1/3] dt-bindings: display: Add GlandaGPU binding

[Conor Dooley <conor@kernel.org>]

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Hey,

On Tue, Jul 14, 2026 at 12:11:43PM +0200, Leander Kieweg wrote:
> Add Device Tree binding documentation for GlandaGPU, a custom
> FPGA-based 2D display controller.
> 
> Signed-off-by: Leander Kieweg <kieweg.leander@gmail.com>
> ---
>  .../bindings/display/glanda,gpu.yaml          | 49 +++++++++++++++++++
>  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
>  2 files changed, 51 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/glanda,gpu.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/glanda,gpu.yaml b/Documentation/devicetree/bindings/display/glanda,gpu.yaml
> new file mode 100644
> index 000000000..40304e773
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/glanda,gpu.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/glanda,gpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: GlandaGPU 2D Hardware Accelerated Display Controller
> +
> +maintainers:
> +  - Leander Kieweg <kieweg.leander@gmail.com>
> +
> +description: |
> +  GlandaGPU is a custom FPGA soft-IP core providing a simple

Sadly googling this device only shows up Phoronix and other copy-paste
reporting sites. I think it'd probably be good to include a link to your
project either here or in the commit message.

> +  2D hardware-accelerated drawing engine (clear/rect/line) with a
> +  VGA-compatible display output. The register window covers a
> +  combined VRAM + MMIO region, with MMIO registers at a fixed
> +  offset within it.
> +
> +properties:
> +  compatible:
> +    const: glanda,gpu-1.0
> +
> +  reg:
> +    maxItems: 1
> +    description:
> +      Combined VRAM + MMIO register window (VRAM at offset 0,
> +      MMIO registers at offset 0x00200000 within this range).
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +    description: Bus and pixel clock provided to the FPGA IP.

This clock sounds like it is actually required? Doubt the device works
without it!
pw-bot: changes-requested

> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    gpu@c0000000 {
> +        compatible = "glanda,gpu-1.0";
> +        reg = <0xc0000000 0x1000000>;
> +        interrupts = <0 43 4>;

Usually I would say do not include things if you don't have to, but I
would much rather you did if the alternative is an interrupts property
like this that doesn't resemble anything used in devicetrees.

> +        clocks = <&osc1>;
> +    };
> \ No newline at end of file
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index b1af9deac..b8b7a5401 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -666,6 +666,8 @@ patternProperties:
>      description: Giantplus Technology Co., Ltd.
>    "^gira,.*":
>      description: Gira Giersiepen GmbH & Co. KG
> +  "^glanda,.*":
> +    description: GlandaGPU
>    "^glinet,.*":
>      description: GL Intelligence, Inc.
>    "^globalscale,.*":
> -- 
> 2.43.0
> 

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