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Thu, 16 Jul 2026 12:30:30 -0700 (PDT) X-Received: by 2002:a05:6a20:6a09:b0:3c0:9c19:65a4 with SMTP id adf61e73a8af0-3c36c465036mr9190040637.76.1784230230267; Thu, 16 Jul 2026 12:30:30 -0700 (PDT) Received: from hu-mdsor-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3140e6c2b17sm21468394eec.25.2026.07.16.12.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 12:30:29 -0700 (PDT) From: mohit.dsor@oss.qualcomm.com Date: Fri, 17 Jul 2026 01:00:13 +0530 Subject: [PATCH v2 1/2] arm64: dts: qcom: shikra-iqs-evk: Add LT9611UXD HDMI bridge support Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260717-shikra-work-v2-1-86ae8552259e@oss.qualcomm.com> References: <20260717-shikra-work-v2-0-86ae8552259e@oss.qualcomm.com> In-Reply-To: <20260717-shikra-work-v2-0-86ae8552259e@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, Mohit Dsor , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, venkata.valluru@oss.qualcomm.com, Jessica Zhang , Mohit Dsor X-Mailer: b4 0.15.2 X-Proofpoint-ORIG-GUID: -Zr2jT8bJ8w71xUOsvEV7rO0ZjQdnXps X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE2MDE5OSBTYWx0ZWRfX0l0XXz2Fv7DH EqByFlZslt9L3MorT5DiZDPdftyxXG29zp6a4QFvJR9YYBU5IDPVMxqSq63O3LVaUVIKRqlXcvH MAa/GIplQpx3J5tb0kfFztsYn3GOwNg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE2MDE5OSBTYWx0ZWRfXyueRRGHf/ihI ha7TB5mdudLtqEjVtd5iUw12eq7NVx9JfLVPsW0ejdDcLiprrJibSn0NjeFsqYZ5hz79bdAqp8O KehypDBBD0u/dswLNzp0AaXUYqgI7tmTjaGt6aAtcqiuSf6Z3+rkq002qu/faeyQ6pvOGM+ZoJp 1/LLcxm2kkLpu08OAn0Q76mM81YcAjgAzOyKPttOevHqGlZ73unAVbJlFbqvz9We8hMqQMKgc0e eqtYnS+Goku8eomzLAGCDRh5Ymn7syKz+JibVJFfVCTEZQ2z0NFPync3f6nh8E8TZqp1z5fl5Lg ZWV3/6Fjzh/ROZCmZbmlRo9m17pRT/ct9i4JV+MwkvY9BTAd+WN5mKcCfRDosbrFroWGAe51Wmy juT+hS/CiBOHx59/ETu+uHvRDBwMToNlD9cw+PrtaQNVLkV0rtU8zdtdGyhCowGYnCnh+1g8h27 QaBnO7qpTeahCwbd7uw== X-Authority-Analysis: v=2.4 cv=NcTWEWD4 c=1 sm=1 tr=0 ts=6a593157 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=Dh2IlRrSrxxA8ivr3KQA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: -Zr2jT8bJ8w71xUOsvEV7rO0ZjQdnXps X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-16_06,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607160199 From: Mohit Dsor Enable the Shikra MDSS display subsystem on the Qualcomm Shikra IQS EVK board and add the Lontium LT9611UXD DSI-to-HDMI bridge node. The LT9611UXD is connected via I2C (bus 4, address 0x41), powered by a GPIO-controlled 3.3V regulator (PM8150 GPIO4) and an always-on 1.8V rail. Reset is on GPIO76 and interrupt on GPIO85. The bridge receives DSI output from MDSS and drives an HDMI-A connector, with the link wired as: DPU -> DSI0 -> LT9611UXD -> HDMI. Signed-off-by: Mohit Dsor --- arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 118 ++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 3a6962388dfd..9e602b5d4776 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -7,6 +7,8 @@ #include "shikra-iqs-som.dtsi" #include "shikra-evk.dtsi" +#include +#include / { model = "Qualcomm Technologies, Inc. Shikra IQS EVK"; @@ -21,6 +23,107 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + vreg_lt9611_vcc: regulator-lt9611-vcc { + compatible = "regulator-fixed"; + regulator-name = "lt9611_vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&hdmi_reg_en>; + pinctrl-names = "default"; + }; + + vreg_lt9611_vdd: regulator-lt9611-vdd { + compatible = "regulator-fixed"; + regulator-name = "lt9611_vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&i2c4 { + status = "okay"; + + lt9611uxd: lt9611uxd@41 { + compatible = "lontium,lt9611uxd"; + reg = <0x41>; + interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 76 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_lt9611_vcc>; + vdd-supply = <&vreg_lt9611_vdd>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8150_l11>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pm8150_gpios { + hdmi_reg_en: hdmi-reg-en-state { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-disable; + }; +}; + +&pm8150_l11 { + /* DSI VDDA - must be at NOM voltage for PHY PLL lock */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + regulator-allow-set-load; }; &remoteproc_cdsp { @@ -64,4 +167,19 @@ &tlmm { <30 2>, /* NFC SPI */ <138 1>, /* NFC Secure IO */ <155 11>; /* eMMC Boot */ + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; }; + -- 2.34.1