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Thu, 16 Jul 2026 14:36:02 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Fri, 17 Jul 2026 00:35:39 +0300 Subject: [PATCH v7 03/13] dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260717-zx29clk-v7-3-408411cfcf36@gmail.com> References: <20260717-zx29clk-v7-0-408411cfcf36@gmail.com> In-Reply-To: <20260717-zx29clk-v7-0-408411cfcf36@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This controller contains clocks and resets for high speed devices on the zx297520v3 board and hardware spinlocks that I expect will be necessary to communicate correctly with the LTE DSP firmware blob. I don't know much about the hwlocks yet other than that they exist, so there is no header yet adding meaning to their indices. Presumably that meaning doesn't exist in hardware and is de facto defined by ZTE's firmware blobs running on the rprocs. A simple MFD driver will instantiate independent clock, reset and hwlock drivers. Signed-off-by: Stefan Dösinger --- v6->v7: *) Moved it back to clock/ *) Remove syscon compatible again. I looked into remaining unknown registers and I am convinced that there is no odd misc register left that can't be exposed as a proper subsystem provider. The controls in 0x100 that ZTE's DRAM reading code exercises are auto clock gating controls and the actual mailbox is in a different controller. Unknown registers in 0x120-0x12c are a frequency voting mechanism for the AXI bus clock. The driver will participate in that voting rather than set the frequency via 0x0. If need be it could be exposed as #interconnect-cells, but it won't necessitate "syscon". *) Reduce the number of input clocks to match register controls in topclk's input control that affect matrix and LSP. *) Add DDR mux and gates. Not to change them, but to make sure CCF knows about which PLL is feeding the sysmem memory Changes v5->v6: Add syscon compatible - Conor suggested this after v4 and I forgot it in v5. v4->v5: Move binding to soc/zte Remove topclk from the example Add #hwlock-cells for hw spinlock registers Add more clocks I stumbled into: sram0 and another LTE related device v3->v4: Split matrixclk into its own controller again because syscon/regmap deals poorly with device nodes that have more than one memory region. As a consequence I am passing all PLL outputs generated on Topclk down to Matrixclk. --- .../bindings/clock/zte,zx297520v3-matrixcrm.yaml | 91 ++++++++++++++++++++++ MAINTAINERS | 1 + include/dt-bindings/clock/zte,zx297520v3-clk.h | 41 ++++++++++ include/dt-bindings/reset/zte,zx297520v3-reset.h | 12 +++ 4 files changed, 145 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml new file mode 100644 index 000000000000..55b1a42836c7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/zte,zx297520v3-matrixcrm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx297520v3 SoC matrix clock and reset controller + +maintainers: + - Stefan Dösinger + +description: | + This controller contains clock and reset controls for high speed devices on + the zx297520v3 board: The CPU, RAM, SDIO and Ethernet clocks and resets are + found here. This controller requires PLL-generated clocks from Topcrm as well + as the fixed 26 MHz and 32 KHz oscillators found on this board. + + This controller also contains hardware mutex registers for synchronization + with different processors on this board. + + All available clocks are defined as preprocessor macros in the + "include/dt-bindings/clock/zte,zx297520v3-clk.h" header. Resets are defined in + the "include/dt-bindings/reset/zte,zx297520v3-reset.h" header. + +properties: + compatible: + const: zte,zx297520v3-matrixcrm + + reg: + maxItems: 1 + + clocks: + items: + - description: 26 MHz external oscillator + - description: 32 KHz external oscillator + - description: Main PLL output from topcrm (usually 624 MHz) + - description: Main PLL subdivision factor 5 + - description: Dpll output from topcrm (usually 491.52 MHz) + - description: Gpll output from topcrm (usually 200 MHz) + - description: Gpll subdivision factor 2 + - description: osc26m work clock from topcrm + + clock-names: + items: + - const: osc26m + - const: osc32k + - const: mpll + - const: mpll-d5 + - const: dpll + - const: gpll + - const: gpll-d2 + - const: wclk-osc26m + + "#clock-cells": + const: 1 + + "#hwlock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#hwlock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + clock-controller@1306000 { + compatible = "zte,zx297520v3-matrixcrm"; + reg = <0x01306000 0x400>; + clocks = <&osc26m>, <&osc32k>, + <&topcrm ZX297520V3_MPLL>, <&topcrm ZX297520V3_MPLL_D5>, + <&topcrm ZX297520V3_DPLL>, <&topcrm ZX297520V3_GPLL>, + <&topcrm ZX297520V3_GPLL_D2>, <&topcrm ZX297520V3_GATED_OSC26M>; + clock-names = "osc26m", "osc32k", "mpll", "mpll-d5", "dpll", + "gpll", "gpll-d2", "wclk-osc26m"; + #clock-cells = <1>; + #hwlock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5f962b9947ab..6d153d2cba79 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3878,6 +3878,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Odd fixes F: Documentation/arch/arm/zte/ F: Documentation/devicetree/bindings/arm/zte.yaml +F: Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml F: Documentation/devicetree/bindings/phy/zte,zx297520v3-usb-phy.yaml F: arch/arm/boot/dts/zte/ diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h index 1f010ff4e6ca..09ee3de679d9 100644 --- a/include/dt-bindings/clock/zte,zx297520v3-clk.h +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h @@ -63,4 +63,45 @@ #define ZX297520V3_HSIC_WCLK 55 #define ZX297520V3_HSIC_PCLK 56 +#define ZX297520V3_SYS_TIMER_WCLK 1 +#define ZX297520V3_CPU_WCLK 2 +#define ZX297520V3_CPU_PCLK 3 +#define ZX297520V3_ZSP_WCLK 4 +#define ZX297520V3_DDR_CTRL_PCLK 5 +#define ZX297520V3_DDR_CTRL_WCLK 6 +#define ZX297520V3_EDCP_WCLK 7 +#define ZX297520V3_EDCP_PCLK 8 +#define ZX297520V3_SD0_WCLK 9 +#define ZX297520V3_SD0_PCLK 10 +#define ZX297520V3_SD0_CDET 11 +#define ZX297520V3_SD1_WCLK 12 +#define ZX297520V3_SD1_PCLK 13 +#define ZX297520V3_SD1_CDET 14 +#define ZX297520V3_NAND_WCLK 15 +#define ZX297520V3_NAND_PCLK 16 +#define ZX297520V3_DMA_PCLK 17 +#define ZX297520V3_MBOX_PCLK 18 +#define ZX297520V3_PDCFG_WCLK 19 +#define ZX297520V3_PDCFG_PCLK 20 +#define ZX297520V3_SSC_WCLK 21 +#define ZX297520V3_SSC_PCLK 22 +#define ZX297520V3_AXI_WCLK 23 +#define ZX297520V3_GMAC_WCLK 24 +#define ZX297520V3_GMAC_PCLK 25 +#define ZX297520V3_GMAC_AHB 26 +#define ZX297520V3_VOU_WCLK 27 +#define ZX297520V3_VOU_PCLK 28 +#define ZX297520V3_LSP_MPLL_D5_WCLK 29 +#define ZX297520V3_LSP_MPLL_D4_WCLK 30 +#define ZX297520V3_LSP_MPLL_D6_WCLK 31 +#define ZX297520V3_LSP_MPLL_D8_WCLK 32 +#define ZX297520V3_LSP_MPLL_D12_WCLK 33 +#define ZX297520V3_LSP_OSC26M_WCLK 34 +#define ZX297520V3_LSP_OSC32K_WCLK 35 +#define ZX297520V3_LSP_PCLK 36 +#define ZX297520V3_LSP_TDM_WCLK 37 +#define ZX297520V3_LSP_DPLL_D4_WCLK 38 +#define ZX297520V3_SRAM0_PCLK 39 +#define ZX297520V3_GSM_CFG_PCLK 40 + #endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */ diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h index 43db72bb59de..4682d4a599c6 100644 --- a/include/dt-bindings/reset/zte,zx297520v3-reset.h +++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h @@ -29,4 +29,16 @@ #define ZX297520V3_HSIC_PHY_RESET 20 #define ZX297520V3_HSIC_RESET 21 +#define ZX297520V3_CPU_RESET 0 +#define ZX297520V3_DDR_CTRL_RESET 1 +#define ZX297520V3_EDCP_RESET 2 +#define ZX297520V3_SD0_RESET 3 +#define ZX297520V3_SD1_RESET 4 +#define ZX297520V3_NAND_RESET 5 +#define ZX297520V3_PDCFG_RESET 6 +#define ZX297520V3_SSC_RESET 7 +#define ZX297520V3_GMAC_RESET 8 +#define ZX297520V3_VOU_RESET 9 +#define ZX297520V3_LSP_RESET 10 + #endif /* __DT_BINDINGS_RESET_ZX297520V3_H */ -- 2.54.0