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From: sashiko-bot@kernel.org
To: muhammad.nazim.amirul.nazle.asmade@altera.com
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v4 2/4] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board
Date: Fri, 17 Jul 2026 02:20:43 +0000	[thread overview]
Message-ID: <20260717022043.9C2241F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260716021932.20037-3-muhammad.nazim.amirul.nazle.asmade@altera.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing driver implementation for 'altr,socfpga-stmmac-agilex5-tsn' results in double RGMII delays and broken networking on gmac1.
--

--- Patch [2]: [PATCH v4 2/4] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board ---
commit ff8022a3fa72ba16d067ef0799f67eb51b957387
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board

This commit adds the device tree for the Intel SoCFPGA Agilex5 SoCDK TSN
Config2 board variant, enabling gmac1 as a TSN port. The commit message
states that a board-specific compatible string is used so the driver can
detect the converter and strip the delay bits before configuring the PHY.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts

[ ... ]

> +&gmac1 {
> +	status = "okay";
> +	compatible = "altr,socfpga-stmmac-agilex5-tsn",
> +		     "altr,socfpga-stmmac-agilex5",
> +		     "snps,dwxgmac-2.10";
> +	phy-mode = "rgmii-id";

[Severity: Medium]
Is the driver support for "altr,socfpga-stmmac-agilex5-tsn" included in
another patch in this series, or already present in the tree?

If the driver implementation is missing, OF will fall back to
"altr,socfpga-stmmac-agilex5". Since the fallback lacks the board-specific
logic to strip the delay bits from the "rgmii-id" phy-mode before passing it
to the PHY driver, will this cause both the PHY driver and the FPGA soft IP
to independently add clock delays? This double-delaying of the RGMII clocks
could violate RGMII timing specifications and cause broken networking on
the gmac1 interface.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260716021932.20037-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2

  reply	other threads:[~2026-07-17  2:20 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-16  2:19 [PATCH v4 0/4] Add Agilex5 SoCDK TSN Config2 board support muhammad.nazim.amirul.nazle.asmade
2026-07-16  2:19 ` [PATCH v4 1/4] dt-bindings: arm: altera: Add Agilex5 SoCDK TSN Config2 board muhammad.nazim.amirul.nazle.asmade
2026-07-16  2:19 ` [PATCH v4 2/4] arm64: dts: socfpga: agilex5: Add " muhammad.nazim.amirul.nazle.asmade
2026-07-17  2:20   ` sashiko-bot [this message]
2026-07-16  2:19 ` [PATCH v4 3/4] dt-bindings: net: altr,socfpga-stmmac: Add altr,socfpga-stmmac-agilex5-tsn compatible muhammad.nazim.amirul.nazle.asmade
2026-07-16  7:58   ` Krzysztof Kozlowski
2026-07-16  2:19 ` [PATCH net-next v4 4/4] net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA converter muhammad.nazim.amirul.nazle.asmade
2026-07-16  7:56   ` Krzysztof Kozlowski

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