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Fri, 17 Jul 2026 02:59:05 -0400 (EDT) From: Jiaxing Hu To: heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [PATCH v4 0/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO Date: Fri, 17 Jul 2026 18:59:01 +1200 Message-ID: <20260717065903.2629399-1-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add mainline support for the ArmSoM CM5, an RK3576 compute module, and its CM5-IO carrier board. Patch 1 adds the binding, patch 2 the module dtsi and the carrier dts. The on-module YT8531 PHY has no crystal and needs the SoC 25 MHz reference clock (clk_mac_refout). Ungating it for RGMII needs a small dwmac-rk change sent separately to netdev [1]; the clock is optional so this DTS applies without it. Tested on a CM5-IO: the YT8531 links at 1000 Mbit/s; RK806, HYM8563, eMMC, microSD, the USB3 hub and the PCIe root complex all probe. dtbs_check is clean. Sorry about the v3 traffic: it went out twice because my mail provider accepted the first copy but then held it for hours before delivering, so a resend and the original both landed. That is fixed now. Changes in v4: - Use phy-mode = "rgmii-id" and let the YT8531 add both RGMII delays internally; drop the MAC tx_delay/rx_delay. The PCB does not use long clock lines, so rgmii-id is the correct description, and this matches the other rk3576 boards. Re-tested: link still comes up at 1000 Mbit/s (Andrew Lunn). - Drop the redundant clocks/assigned-clocks on the PHY node; the 25 MHz reference is enabled and rated through clk_mac_refout on the gmac node, and clock properties on an MDIO child are not processed (sashiko-bot). - Enable &sai6, the I2S CPU DAI the HDMI sound card needs to probe (sashiko-bot). - Pick up Krzysztof's Acked-by on patch 1. Changes in v3: - Remove the ES8388 codec from the file header and the i2c0 block comment (the node was dropped in v2 but the comments still named it). - Use gpios instead of gpio in the vcc_3v3_pcie fixed regulator. Changes in v2: - Type-C DP alt-mode: name the altmodes child "displayport" and make svid a /bits/ 16 value; drop the undocumented svid from &usbdp_phy and add the missing mode-switch. - Move the FUSB302 role-switch endpoint into the connector's ports and rename the node to usb-typec@22. - Drop the ES8388 node and the unreferenced gmac0_rst, bt_reg_on and wifi_host_wake_irq pinctrls. - Rename the wifi-poweren-gpio pinctrl node (collided with gpio-consumer.yaml). - Describe the PHY reset at the MDIO bus level rather than with the deprecated snps,reset-gpios. [1] net: stmmac: dwmac-rk: enable the reference clock for output mode Jiaxing Hu (2): dt-bindings: arm: rockchip: Add ArmSoM CM5 and CM5-IO arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO .../devicetree/bindings/arm/rockchip.yaml | 7 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3576-armsom-cm5-io.dts | 402 +++++++++++++ .../boot/dts/rockchip/rk3576-armsom-cm5.dtsi | 558 ++++++++++++++++++ 4 files changed, 968 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi -- 2.43.0