Re: [PATCH 4/4] riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The commit message claims to describe a SPI NOR flash chip on chip select 0, but the corresponding device tree node is absent.
- [Medium] The pinctrl configuration sets the SPI pad voltage to 1.8V, which conflicts with the 3.3V Winbond W25Q64JV SPI NOR flash mentioned in the commit message.
--

--- Patch [4]: [PATCH 4/4] riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX ---
commit 195bf5fbf14f1dbf36d3f0697603287770b0c9db
Author: Zhengyu He <hezhy472013@gmail.com>

riscv: dts: spacemit: enable SPI0 on K3 CoM260-IFX

This commit enables the PDMA controller and SPI0 on the K3 CoM260-IFX board.
It also adds the pinctrl states for the SPI0 pins exposed on the board's 40-pin
header.

> diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
> --- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
> +++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
[ ... ]
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&ssp0_2_cfg>;
> +	status = "okay";
> +};

[Severity: Medium]
The commit message states this patch will "describe the SPI NOR on chip select
0 for the current validation setup", but is the child node for the flash chip
missing here?

> diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
> --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
[ ... ]
> +	/omit-if-no-ref/
> +	ssp0_2_cfg: ssp0-2-cfg {
> +		ssp0-0-pins {
> +			pinmux = <K3_PADCONF(104, 1)>,  /* ssp0 tx */
> +				 <K3_PADCONF(105, 1)>,  /* ssp0 rx */
> +				 <K3_PADCONF(106, 1)>;  /* ssp0 clk */
> +
> +			bias-disable;
> +			drive-strength = <25>;
> +			power-source = <1800>;

[Severity: Medium]
Does this 1.8V power source configuration match the validation setup described
in the commit message?

The commit message mentions testing with a Winbond W25Q64JV, which is a 3.3V
component (the 1.8V equivalent is the W25Q64JW). If the SoC IO is driving
1.8V signals without a level shifter, it might fail to meet the 3.3V chip's
input high voltage thresholds. Could this be a typo in the commit message, or
is the power-source value incorrect for this board?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-0-969a1b0f783f@gmail.com?part=4