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Sat, 18 Jul 2026 23:46:13 -0400 (EDT) From: Jiaxing Hu To: heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [PATCH v5 0/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO Date: Sun, 19 Jul 2026 15:46:09 +1200 Message-ID: <20260719034611.3623066-1-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add mainline support for the ArmSoM CM5, an RK3576 compute module, and its CM5-IO carrier board. Patch 1 adds the binding, patch 2 the module dtsi and the carrier dts. The on-module YT8531 PHY has no crystal and takes its 25 MHz reference from the SoC. Following review of v4, the reference is now handled the way Andrew Lunn and Maxime Chevallier asked for: the PHY is the consumer and enables the clock itself. That needs a small motorcomm change sent to netdev [1]; the clock is optional so this DTS still applies without it. The earlier dwmac-rk MAC-side patch is dropped. Tested on a CM5-IO with [1] applied: the YT8531 links at 1000 Mbit/s; RK806, HYM8563, eMMC, microSD, the USB3 hub and PCIe all probe. dtbs_check is clean. Changes in v5: - The 25 MHz reference is now consumed by the PHY, not the MAC. The PHY node gets its clock back (clocks = <&cru REFCLKO25M_GMAC0_OUT>) and is named explicitly (ethernet-phy-id4f51.e91b) so it is instantiated from the DT without an MDIO ID probe, which it cannot answer before the clock runs. &gmac0 drops clk_mac_refout and inherits the SoC clocks. This reverses the v4 removal of the PHY-node clock, which was the wrong direction. - Enable &sai6, the I2S CPU DAI the HDMI sound card needs (already in v4; re-tested here, HDMI audio card registers). Changes in v4: - phy-mode = "rgmii-id", drop the MAC tx_delay/rx_delay; the PHY adds both delays (Andrew Lunn). Re-tested at 1000 Mbit/s. - Pick up Krzysztof's Acked-by on patch 1. Changes in v3: - Remove the ES8388 codec from the header and the i2c0 comment; use gpios in the vcc_3v3_pcie regulator. Changes in v2: - Fix the Type-C DP alt-mode node, move the FUSB302 role-switch endpoint into the connector, drop the ES8388 node and dead pinctrls, rename the wifi pinctrl node, and describe the PHY reset at the MDIO bus level. [1] net: phy: motorcomm: enable the reference clock for YT8531 Jiaxing Hu (2): dt-bindings: arm: rockchip: Add ArmSoM CM5 and CM5-IO arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO .../devicetree/bindings/arm/rockchip.yaml | 7 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3576-armsom-cm5-io.dts | 402 +++++++++++++ .../boot/dts/rockchip/rk3576-armsom-cm5.dtsi | 558 ++++++++++++++++++ 4 files changed, 968 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi -- 2.43.0