From: sashiko-bot@kernel.org
To: "Dinh Nguyen" <dinguyen@kernel.org>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: edac: altera: agilex5: document new edac support
Date: Mon, 20 Jul 2026 20:21:43 +0000 [thread overview]
Message-ID: <20260720202144.4E2461F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260720201425.1538771-2-dinguyen@kernel.org>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Removing `maxItems: 2` from the global `interrupts` property to allow up to 7 items relaxes constraints for older hardware generations, allowing them to improperly specify up to 7 interrupts and bypass schema validation.
- [Medium] The `interrupt-names` property is introduced for the new `altr,socfpga-agilex5-ecc-manager` variant, but it is not conditionally enforced as a required property for Agilex5.
--
--- Patch [1]: [PATCH 1/4] dt-bindings: edac: altera: agilex5: document new edac support ---
commit d266055949125966c496511b166440e55892f101
Author: Dinh Nguyen <dinguyen@kernel.org>
dt-bindings: edac: altera: agilex5: document new edac support
This commit adds EDAC support for Agilex5 peripherals, including SDM QSPI,
CRAM SEU, and IO96B. It updates the device tree bindings to include the new
compatible string and expands the interrupts and interrupt-names properties
to accommodate up to 7 interrupts for the new hardware variant.
> diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
> index 136e8fccd429a..2ccb0f2163185 100644
> --- a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
> +++ b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
[ ... ]
> @@ -33,7 +36,25 @@ properties:
>
> interrupts:
> minItems: 1
> - maxItems: 2
> + items:
> + - description: Global single-bit error
> + - description: Global double-bit error
> + - description: IO96B0 DRAM controller error
> + - description: IO96B1 DRAM controller error
> + - description: SDM QSPI single-bit error
> + - description: SDM QSPI double-bit error
> + - description: SDM single-event
[Severity: Medium]
Does removing the maxItems: 2 constraint here allow older hardware generations
(like S10 or A10) to mistakenly define up to 7 interrupts and silently pass
schema validation?
Should the binding use an allOf / if-then block to enforce maxItems: 2
specifically for the older compatibles?
> +
> + interrupt-names:
> + minItems: 1
> + items:
> + - const: global_sbe
> + - const: global_dbe
> + - const: io96b0
> + - const: io96b1
> + - const: sdm_qspi_sbe
> + - const: sdm_qspi_dbe
> + - const: sdm_seu
[Severity: Medium]
Will this allow device trees for Agilex5 to silently pass schema validation
even if they omit the interrupt-names entirely?
Should there be a conditional block enforcing interrupt-names as a required
property specifically for the altr,socfpga-agilex5-ecc-manager variant?
>
> interrupt-controller: true
>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260720201425.1538771-1-dinguyen@kernel.org?part=1
next prev parent reply other threads:[~2026-07-20 20:21 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-20 20:14 [PATCH 0/4] EDAC/altera: Add support for Agilex5 platform Dinh Nguyen
2026-07-20 20:14 ` [PATCH 1/4] dt-bindings: edac: altera: agilex5: document new edac support Dinh Nguyen
2026-07-20 20:21 ` sashiko-bot [this message]
2026-07-20 20:14 ` [PATCH 2/4] EDAC/altera: use flag to differentiate 64-bit platforms Dinh Nguyen
2026-07-20 20:30 ` sashiko-bot
2026-07-20 20:14 ` [PATCH 3/4] EDAC/altera: Add support for Agilex5 ECC manager Dinh Nguyen
2026-07-20 20:25 ` sashiko-bot
2026-07-20 20:14 ` [PATCH 4/4] arm64: dts: socfpga: agilex5: add support for the " Dinh Nguyen
2026-07-20 20:35 ` sashiko-bot
2026-07-20 20:33 ` [PATCH 0/4] EDAC/altera: Add support for Agilex5 platform Borislav Petkov
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