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Wed, 22 Jul 2026 03:34:29 -0400 (EDT) From: Jiaxing Hu To: mchehab@kernel.org, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.dufresne@collabora.com Cc: ezequiel@vanguardiasur.com.ar, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [RFC PATCH 1/3] dt-bindings: media: add Rockchip RK3576 VEPU H.264 encoder Date: Wed, 22 Jul 2026 19:34:15 +1200 Message-ID: <20260722073417.2064667-2-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260722073417.2064667-1-gahing@gahingwoo.com> References: <20260722073417.2064667-1-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the binding for the VEPU510 H.264 hardware video encoder found on the Rockchip RK3576. Each SoC has two independent encoder cores, each behind its own IOMMU. Signed-off-by: Jiaxing Hu --- .../bindings/media/rockchip,rk3576-vepu.yaml | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3576-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3576-vepu.yaml new file mode 100644 index 000000000..942118cb3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip,rk3576-vepu.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,rk3576-vepu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip VEPU510 Video Encoder (RK3576) + +maintainers: + - Jiaxing Hu + +description: |- + RK3576 has two identical VEPU510 hardware H.264/H.265 video encoder + cores. Each core is a standalone V4L2 mem2mem device in this binding; + there is no shared hardware descriptor/link-list engine tying the two + cores together (unlike the RK3576 video decoder's CCU), so each core + node is independent and self-contained. + +properties: + compatible: + const: rockchip,rk3576-vepu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The Video Encoder AXI interface clock + - description: The Video Encoder AHB interface clock + - description: The Video Encoder core clock + + clock-names: + items: + - const: aclk_vcodec + - const: hclk_vcodec + - const: clk_core + + assigned-clocks: true + + assigned-clock-rates: true + + resets: + items: + - description: The Video Encoder AXI interface reset + - description: The Video Encoder AHB interface reset + - description: The Video Encoder core reset + + reset-names: + items: + - const: video_a + - const: video_h + - const: video_core + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - iommus + +additionalProperties: false + +examples: + - | + #include + #include + #include + + vepu0: video-codec@27a00000 { + compatible = "rockchip,rk3576-vepu"; + reg = <0x27a00000 0x6000>; + interrupts = ; + clocks = <&cru ACLK_VEPU0>, <&cru HCLK_VEPU0>, <&cru CLK_VEPU0_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + assigned-clocks = <&cru ACLK_VEPU0>, <&cru CLK_VEPU0_CORE>; + assigned-clock-rates = <400000000>, <702000000>; + resets = <&cru SRST_A_VEPU0>, <&cru SRST_H_VEPU0>, <&cru SRST_VEPU0_CORE>; + reset-names = "video_a", "video_h", "video_core"; + power-domains = <&power RK3576_PD_VEPU0>; + iommus = <&vepu0_mmu>; + }; + +... -- 2.43.0