On Thu, Jul 23, 2026 at 06:45:41PM +0300, Laurent Pinchart wrote:
> On Thu, Jul 23, 2026 at 01:01:11PM +0200, Richard Leitner wrote:
> > On Wed, Jul 22, 2026 at 11:03:09PM +0100, Mark Brown wrote:
> > > On Wed, Jul 22, 2026 at 11:58:46PM +0200, Richard Leitner wrote:
> > > 
> > > > @Mark: I understood that if the fpga really intercepts the I2C bus, it
> > > > should be modelled accordingly in device tree. But what would be the
> > > > preferred implementation if both devices sit on the same I2C bus, but
> > > > one is messing up some register reads on purpose?
> > > 
> > > I think we would need to have a coherent understanding and description
> > > of the actual issue to know how to describe it.
> > 
> > Understood. I will try to figure out how the hardware is really wired
> > and come back to you.
> 
> Based on the information I have received so far, the FPGA is interposed
> between the host and sensor. It could therefore be modelled in DT as
> child of the I2C bus and a parent of the sensor.
> 
> New version of some of the Vision Components modules have fixed the
> multi-read bug, so we will still need a property in the FPGA DT node to
> indicate if the quirk should be activated.

Or come up with a compatible for the FPGA DT node that uniquely
identifies the revision of the RTL in use.
That's my preference for things that use some custom RTL that aren't
configuration parameters.

> 
> > > Please do not add random characters to my name.
> > 
> > Sorry, I didn’t mean any harm.
> 
> -- 
> Regards,
> 
> Laurent Pinchart