[PATCH net-next 3/7] dt-bindings: net: xlnx,axi-ethernet: Add 10G/25G (XXV) ethernet

[Suraj Gupta <suraj.gupta2@amd.com>]

The XXV Ethernet IP integrates a 10G/25G Ethernet MAC with an in-core
PCS/PMA driving a high-speed serial transceiver. Extend the existing
xlnx,axi-ethernet binding to describe it.

Add the "xlnx,xxv-ethernet-1.0" compatible and make the resource
requirements conditional based on the XXV compatible string:

  - "dmas", "dma-names", and "phy-mode" are required.
  - Interrupt properties are not required as it does not have a dedicated
    Ethernet core interrupt.
  - "phy-handle" is not required as it has internal PCS and PMA.
  - Add the 10gbase-r and 25gbase-r phy-mode values used by XXV.
Annotate the existing compatibles, generalise the title to cover both
variants, and add an example node for XXV.

Define properties at top level per binding style and use if/then to
constrain requirements and phy-mode per compatible. Forbid 1G-only and
unused ethernet-controller properties on XXV nodes.

Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
 .../bindings/net/xlnx,axi-ethernet.yaml       | 144 ++++++++++++++----
 1 file changed, 117 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
index fb02e579463c..23b1a27c04e5 100644
--- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
+++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
@@ -4,36 +4,46 @@
 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: AXI 1G/2.5G Ethernet Subsystem
+title: Xilinx AXI Ethernet Subsystem
 
 description: |
-  Also called  AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
-  provides connectivity to an external ethernet PHY supporting different
-  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
-  segments of memory for buffering TX and RX, as well as the capability of
-  offloading TX/RX checksum calculation off the processor.
+  This binding describes Xilinx AXI Ethernet subsystem IPs, including the
+  AXI 1G/2.5G Ethernet Subsystem and the 10G/25G (XXV) Ethernet Subsystem.
+
+  The AXI 1G/2.5G Ethernet Subsystem provides connectivity to an external
+  ethernet PHY supporting different interfaces: MII, GMII, RGMII, SGMII,
+  1000BaseX. It also includes two segments of memory for buffering TX and RX,
+  as well as the capability of offloading TX/RX checksum calculation off the
+  processor.
 
   Management configuration is done through the AXI interface, while payload is
   sent and received through means of an AXI DMA controller. This driver
   includes the DMA driver code, so this driver is incompatible with AXI DMA
   driver.
 
+  The XXV Ethernet Subsystem integrates a 10G/25G Ethernet MAC and PCS/PMA
+  connected to a high-speed serial transceiver. It supports the 10GBASE-R and
+  25GBASE-R line rates, with 25G operation following the 25G Ethernet
+  Consortium specification. Its payload is moved by an external AXI DMA
+  controller rather than a DMA engine integrated into the MAC.
+
 maintainers:
   - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
 
 properties:
   compatible:
     enum:
-      - xlnx,axi-ethernet-1.00.a
-      - xlnx,axi-ethernet-1.01.a
-      - xlnx,axi-ethernet-2.01.a
+      - xlnx,axi-ethernet-1.00.a # AXI 1G/2.5G Ethernet Subsystem
+      - xlnx,axi-ethernet-1.01.a # AXI 1G/2.5G Ethernet Subsystem
+      - xlnx,axi-ethernet-2.01.a # AXI 1G/2.5G Ethernet Subsystem
+      - xlnx,xxv-ethernet-1.0 # 10G/25G Ethernet Subsystem
 
   reg:
     description:
-      Address and length of the IO space, as well as the address
-      and length of the AXI DMA controller IO space, unless
-      axistream-connected is specified, in which case the reg
-      attribute of the node referenced by it is used.
+      Address and length of the IO space. For AXI 1G/2.5G using the legacy
+      embedded DMA, this also covers the AXI DMA controller IO space, unless
+      axistream-connected is specified, in which case the reg attribute of
+      the node referenced by it is used.
     minItems: 1
     maxItems: 2
 
@@ -62,6 +72,8 @@ properties:
       - rgmii
       - sgmii
       - 1000base-x
+      - 10gbase-r
+      - 25gbase-r
 
   xlnx,phy-type:
     description:
@@ -93,19 +105,12 @@ properties:
       selected on core reset (i.e. by the basex_or_sgmii core input line).
 
   clocks:
-    items:
-      - description: Clock for AXI register slave interface.
-      - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
-      - description: Ethernet reference clock, used by signal delay primitives
-                     and transceivers.
-      - description: MGT reference clock (used by optional internal PCS/PMA PHY)
+    minItems: 3
+    maxItems: 4
 
   clock-names:
-    items:
-      - const: s_axi_lite_clk
-      - const: axis_clk
-      - const: ref_clk
-      - const: mgt_clk
+    minItems: 3
+    maxItems: 4
 
   axistream-connected:
     $ref: /schemas/types.yaml#/definitions/phandle
@@ -139,15 +144,88 @@ properties:
 
 required:
   - compatible
-  - interrupts
   - reg
   - xlnx,rxmem
-  - phy-handle
 
 allOf:
   - $ref: /schemas/net/ethernet-controller.yaml#
 
-additionalProperties: false
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - xlnx,axi-ethernet-1.00.a
+              - xlnx,axi-ethernet-1.01.a
+              - xlnx,axi-ethernet-2.01.a
+    then:
+      required:
+        - interrupts
+        - phy-handle
+      properties:
+        phy-mode:
+          enum:
+            - mii
+            - gmii
+            - rgmii
+            - sgmii
+            - 1000base-x
+        clocks:
+          items:
+            - description: Clock for AXI register slave interface.
+            - description: AXI4-Stream clock for TXD RXD TXC and RXS
+                           interfaces.
+            - description: Ethernet reference clock, used by signal delay
+                           primitives and transceivers.
+            - description: MGT reference clock (used by optional internal
+                           PCS/PMA PHY)
+        clock-names:
+          items:
+            - const: s_axi_lite_clk
+            - const: axis_clk
+            - const: ref_clk
+            - const: mgt_clk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: xlnx,xxv-ethernet-1.0
+    then:
+      required:
+        - dmas
+        - dma-names
+        - phy-mode
+        - clocks
+        - clock-names
+      properties:
+        phy-mode:
+          enum:
+            - 10gbase-r
+            - 25gbase-r
+        interrupts: false
+        phy-handle: false
+        pcs-handle: false
+        axistream-connected: false
+        xlnx,phy-type: false
+        xlnx,txcsum: false
+        xlnx,rxcsum: false
+        xlnx,switch-x-sgmii: false
+        mdio: false
+        clocks:
+          maxItems: 3
+          items:
+            - description: RX AXI4-Stream clock (rx_core_clk).
+            - description: GT DRP clock (dclk).
+            - description: AXI4-Lite register clock (s_axi_aclk).
+        clock-names:
+          maxItems: 3
+          items:
+            - const: rx_core_clk
+            - const: dclk
+            - const: s_axi_aclk
+
+unevaluatedProperties: false
 
 examples:
   - |
@@ -198,3 +276,15 @@ examples:
             };
         };
     };
+
+  - |
+    ethernet@80000000 {
+        compatible = "xlnx,xxv-ethernet-1.0";
+        reg = <0x80000000 0x10000>;
+        clock-names = "rx_core_clk", "dclk", "s_axi_aclk";
+        clocks = <&rx_clk>, <&drp_clk>, <&axi_clk>;
+        dma-names = "tx_chan0", "rx_chan0";
+        dmas = <&axi_dma 0>, <&axi_dma 1>;
+        phy-mode = "25gbase-r";
+        xlnx,rxmem = <0x8000>;
+    };
-- 
2.25.1